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path: root/lib/Target/PowerPC/PPCISelLowering.cpp
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2006-11-17start using PPC predicates more consistently.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31833 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-16This is a general clean up of the PowerPC ABI. Address several problems andJim Laskey
bugs including making sure that the TOS links back to the previous frame, that the maximum call frame size is not included twice when using frame pointers, no longer growing the frame on calls, double storing of SP and a cleaner/faster dynamic alloca. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31792 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-15fix ldu/stu jit encoding. Swith 64-bit preinc load instrs to use memriChris Lattner
addrmodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31757 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-14lower "X = seteq Y, Z" to '(shr (ctlz (xor Y, Z)), 5)' instead ofChris Lattner
'(shr (ctlz (sub Y, Z)), 5)'. The use of xor better exposes the operation to bit-twiddling logic in the dag combiner. For example, this: typedef struct { unsigned prefix : 4; unsigned code : 4; unsigned unsigned_p : 4; } tree_common; int foo(tree_common *a, tree_common *b) { return a->code == b->code; } Now compiles to: _foo: lwz r2, 0(r4) lwz r3, 0(r3) xor r2, r3, r2 rlwinm r2, r2, 28, 28, 31 cntlzw r2, r2 srwi r3, r2, 5 blr instead of: _foo: lbz r2, 3(r4) lbz r3, 3(r3) srwi r2, r2, 4 srwi r3, r3, 4 subf r2, r2, r3 cntlzw r2, r2 srwi r3, r2, 5 blr saving a cycle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31725 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-14minor tweaks, reject vector preinc.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31717 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-11ppc64 doesn't have lwau, don't attempt to form it.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31656 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-10implement preinc support for r+i loads on ppc64Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31654 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-10add an initial cut at preinc loads for ppc32. This is broken for ppc64Chris Lattner
(because the 64-bit reg target versions aren't implemented yet), doesn't support r+r addr modes, and doesn't handle stores, but it works otherwise. :) This is disabled unless -enable-ppc-preinc is passed to llc for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31621 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-09PPC supports i32 / i64 pre-inc load / store.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31599 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-09Rename ISD::MemOpAddrMode to ISD::MemIndexedModeEvan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31595 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-08Refactor all the addressing mode selection stuff into the isel loweringChris Lattner
class, where it can be used for preinc formation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31536 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-02For PR786:Reid Spencer
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting fall out by removing unused variables. Remaining warnings have to do with unused functions (I didn't want to delete code without review) and unused variables in generated code. Maintainers should clean up the remaining issues when they see them. All changes pass DejaGnu tests and Olden. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31380 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-02Implement the getRegForInlineAsmConstraint method for PPC. With recentChris Lattner
sdisel changes, this eliminates a ton of copies around common inline asms. For example: int test2(int Y, int X) { asm("foo %0, %1" : "=r"(X): "r"(X)); return X; } now compiles to: _test2: foo r3, r4 blr instead of: _test2: mr r2, r4 foo r2, r2 mr r3, r2 blr GCC produces: _test2: foo r4, r4 mr r3,r4 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31367 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-31Change the prototype for TargetLowering::isOperandValidForConstraintChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31318 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-30All targets expand BR_JT for now.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31294 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-18set the ppc64 stack pointer right, dynamic alloca now works for ppc64Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31028 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-18Expand alloca for ppc64Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31027 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-13Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30945 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-09Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30844 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-05Make use of getStore().Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30759 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-04Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add anEvan Cheng
extra operand to LOADX to specify the exact value extension type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30714 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-20Legalize is no longer limited to cleverness with just constant shift amounts.Chris Lattner
Allow it to be clever when possible and fall back to the gross code when needed. This allows us to compile: long long foo1(long long X, int C) { return X << (C|32); } long long foo2(long long X, int C) { return X << (C&~32); } to: _foo1: rlwinm r2, r5, 0, 27, 31 slw r3, r4, r2 li r4, 0 blr .globl _foo2 .align 4 _foo2: rlwinm r2, r5, 0, 27, 25 subfic r5, r2, 32 slw r3, r3, r2 srw r5, r4, r5 or r3, r3, r5 slw r4, r4, r2 blr instead of: _foo1: ori r2, r5, 32 subfic r5, r2, 32 addi r6, r2, -32 srw r5, r4, r5 slw r3, r3, r2 slw r6, r4, r6 or r3, r3, r5 slw r4, r4, r2 or r3, r3, r6 blr .globl _foo2 .align 4 _foo2: rlwinm r2, r5, 0, 27, 25 subfic r5, r2, 32 addi r6, r2, -32 srw r5, r4, r5 slw r3, r3, r2 slw r6, r4, r6 or r3, r3, r5 slw r4, r4, r2 or r3, r3, r6 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30507 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-19Fold the PPCISD shifts when presented with 0 inputs. This occurs for codeChris Lattner
like: long long test(long long X, int Y) { return 1ULL << Y; } long long test2(long long X, int Y) { return -1LL << Y; } which we used to compile to: _test: li r2, 1 subfic r3, r5, 32 li r4, 0 addi r6, r5, -32 srw r3, r2, r3 slw r4, r4, r5 slw r6, r2, r6 or r3, r4, r3 slw r4, r2, r5 or r3, r3, r6 blr _test2: li r2, -1 subfic r3, r5, 32 addi r6, r5, -32 srw r3, r2, r3 slw r4, r2, r5 slw r2, r2, r6 or r3, r4, r3 or r3, r3, r2 blr Now we produce: _test: li r2, 1 addi r3, r5, -32 subfic r4, r5, 32 slw r3, r2, r3 srw r4, r2, r4 or r3, r4, r3 slw r4, r2, r5 blr _test2: li r2, -1 subfic r3, r5, 32 addi r6, r5, -32 srw r3, r2, r3 slw r4, r2, r5 slw r2, r2, r6 or r3, r4, r3 or r3, r3, r2 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30479 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-12Reflects MachineConstantPoolEntry changes.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30279 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-28For PR387:Reid Spencer
Close out this long standing bug by removing the remaining overloaded virtual functions in LLVM. The -Woverloaded-virtual option is now turned on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29934 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-12Fix a bug in a recent refactoring that broke a bunch of stuff.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29649 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-11Eliminate use of getNode that takes a vector.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29614 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-11Convert vectors to fixed sized arrays and smallvectors. Eliminate use of ↵Chris Lattner
getNode that takes a vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29609 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-11Fix miscompilation of float vector returns. Compile code to this:Chris Lattner
_func: vsldoi v2, v3, v2, 12 vsldoi v2, v2, v2, 4 blr instead of: _func: vsldoi v2, v3, v2, 12 vsldoi v2, v2, v2, 4 *** vor f1, v2, v2 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29607 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-28Fix some ppc64 issues with vector code.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29384 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-26Rename RelocModel::PIC to PIC_, to avoid conflicts with -DPIC.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29307 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-10Implement Regression/CodeGen/PowerPC/bswap-load-store.ll by folding bswapsChris Lattner
into i16/i32 load/stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29089 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-27Implement 64-bit select, bswap, etc.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28935 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-27PPC doesn't have bit converts to/from i64Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28932 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-27Implement 64-bit undef, sub, shl/shr, srem/uremChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28929 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-27Use i32 for shift amounts instead of i64. This gets bisort working.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28927 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-27Implement a bunch of 64-bit cleanliness work. With this, treeadd builds (butChris Lattner
doesn't work right). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28921 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-26Improve PPC64 calling convention supportChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28919 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-21Correct returns of 64-bit values, though they seemed to work before...Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28892 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-16fix some assumptions that pointers can only be 32-bits. With this, we canChris Lattner
now compile: static unsigned long X; void test1() { X = 0; } into: _test1: lis r2, ha16(_X) li r3, 0 stw r3, lo16(_X)(r2) blr Totally amazing :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28839 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-16Rename some subtarget features. A CPU now can *have* 64-bit instructions,Chris Lattner
can in 32-bit mode we can choose to optionally *use* 64-bit registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28824 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-15Type of extract_element index operand should be iPTR.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28797 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-10Fix a problem exposed by the local allocator. CALL instructions are not markedChris Lattner
as using incoming argument registers, so the local allocator would clobber them between their set and use. To fix this, we give the call instructions a variable number of uses in the CALL MachineInstr itself, so live variables understands the live ranges of these register arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28744 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-30Always reserve space for 8 spilled GPRs. GCC apparently assumes that thisChris Lattner
space will be available, even if the callee isn't varargs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28571 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-26Change RET node to include signness information of the return values. i.e.Evan Cheng
RET chain, value1, sign1, value2, sign2, ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28510 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-25CALL node change (arg / sign pairs instead of just arguments).Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28462 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-24Patches to make the LLVM sources more -pedantic clean. Patch providedChris Lattner
by Anton Korobeynikov! This is a step towards closing PR786. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28447 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-24Fix CodeGen/Generic/vector.ll:test_div with altivec.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28445 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-24Handle SETO* like we handle SET*, restoring behavior after Evan's setccChris Lattner
change. This fixes PowerPC/fnegsel.ll. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-17Make PPC call lowering more aggressive, making the isel matching code simpleChris Lattner
enough to be autogenerated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28354 91177308-0d34-0410-b5e6-96231b3b80d8
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