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Access mips register classes via MCRegisterInfo's functions instead of via the
TargetRegisterClasses defined in MipsGenRegisterInfo.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159953 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159854 91177308-0d34-0410-b5e6-96231b3b80d8
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Include file MipsGenRegisterInfo.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159851 91177308-0d34-0410-b5e6-96231b3b80d8
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Mips specific inline asm operand modifier D.
Comment changes and predicate change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159802 91177308-0d34-0410-b5e6-96231b3b80d8
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Print the second half of a double word operand.
The include list was cleaned up a bit as well.
Also the test case was modified to test for both
big and little patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159787 91177308-0d34-0410-b5e6-96231b3b80d8
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mips32 rev1 (the directives are emitted when target is mips32r2 too).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159770 91177308-0d34-0410-b5e6-96231b3b80d8
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inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed. This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159625 91177308-0d34-0410-b5e6-96231b3b80d8
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it appears to be breaking the bots.
This reverts commit 1b055ce320fa13f6f1ac81670d11b45e01f79876.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159619 91177308-0d34-0410-b5e6-96231b3b80d8
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inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed. This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159610 91177308-0d34-0410-b5e6-96231b3b80d8
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Contributer: Sasa Stankovic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159574 91177308-0d34-0410-b5e6-96231b3b80d8
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This is a preliminary step toward having TargetPassConfig be able to
start and stop the compilation at specified passes for unit testing
and debugging. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159567 91177308-0d34-0410-b5e6-96231b3b80d8
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the comment per code review feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159376 91177308-0d34-0410-b5e6-96231b3b80d8
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following description in the gnu sources:
Print $0 if operand is zero otherwise print the op normally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159324 91177308-0d34-0410-b5e6-96231b3b80d8
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include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h.
The reasoning is because the DebugInfo module is simply an interface to the
debug info MDNodes and has nothing to do with analysis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159312 91177308-0d34-0410-b5e6-96231b3b80d8
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It takes advantage of r159299 which introduces relocation support for N64.
elf-dump needed to be upgraded to support N64 relocations as well.
This passes make check.
Jack
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159302 91177308-0d34-0410-b5e6-96231b3b80d8
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It takes advantage of r159299 which introduces relocation support for N64.
elf-dump needed to be upgraded to support N64 relocations as well.
This passes make check.
Jack
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159301 91177308-0d34-0410-b5e6-96231b3b80d8
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which many Mips 64 ABIs use than for O64 which many
if not all other target ABIs use.
Most architectures have the following 64 bit relocation record format:
typedef struct
{
Elf64_Addr r_offset; /* Address of reference */
Elf64_Xword r_info; /* Symbol index and type of relocation */
} Elf64_Rel;
typedef struct
{
Elf64_Addr r_offset;
Elf64_Xword r_info;
Elf64_Sxword r_addend;
} Elf64_Rela;
Whereas N64 has the following format:
typedef struct
{
Elf64_Addr r_offset;/* Address of reference */
Elf64_Word r_sym; /* Symbol index */
Elf64_Byte r_ssym; /* Special symbol */
Elf64_Byte r_type3; /* Relocation type */
Elf64_Byte r_type2; /* Relocation type */
Elf64_Byte r_type; /* Relocation type */
} Elf64_Rel;
typedef struct
{
Elf64_Addr r_offset;/* Address of reference */
Elf64_Word r_sym; /* Symbol index */
Elf64_Byte r_ssym; /* Special symbol */
Elf64_Byte r_type3; /* Relocation type */
Elf64_Byte r_type2; /* Relocation type */
Elf64_Byte r_type; /* Relocation type */
Elf64_Sxword r_addend;
} Elf64_Rela;
The structure is the same size, but the r_info data element
is now 5 separate elements. Besides the content aspects,
endian byte reordering will be different for the area with
each element being endianized separately.
I treat this as generic and continue to pass r_type as
an integer masking and unmasking the byte sized N64
values for N64 mode. I've implemented this and it causes no
affect on other current targets.
This passes make check.
Jack
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159299 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159243 91177308-0d34-0410-b5e6-96231b3b80d8
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2. re-enable null.ll test
3. fix some minor style violations
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158935 91177308-0d34-0410-b5e6-96231b3b80d8
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to be generic across architectures. It has the
following description in the gnu sources:
Substitute immediate value without immediate syntax
Several Architectures such as x86 have local implementations
of operand modifier 'c' which go beyond the above description
slightly. To make use of the generic modifiers without overriding
local implementation one can make a call to the base class method
for AsmPrinter::PrintAsmOperand() in the locally derived method's
"default" case in the switch statement. That way if it is already
defined locally the generic version will never get called.
This change is needed when test/CodeGen/generic/asm-large-immediate.ll
failed on a native Mips board. The test was assuming a generic
implementation was in place.
Affected files:
lib/Target/Mips/MipsAsmPrinter.cpp:
Changed the default case to call the base method.
lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
Added 'c' to the switch cases.
test/CodeGen/Mips/asm-large-immediate.ll
Mips compiled version of the generic one
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158925 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158855 91177308-0d34-0410-b5e6-96231b3b80d8
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that are generated by TableGen and are already available in
MipsGenRegisterInfo.inc. Suggested by Jakob Stoklund Olesen.
Also, fix bug in function DecodeAFGR64RegisterClass.
Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158846 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158702 91177308-0d34-0410-b5e6-96231b3b80d8
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MipsCodeEmitter.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158701 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158602 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158471 91177308-0d34-0410-b5e6-96231b3b80d8
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being used by Mips16 or Micro Mips
2. clean up a few lines too long encountered
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158470 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158446 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158437 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158436 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158434 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158433 91177308-0d34-0410-b5e6-96231b3b80d8
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as a scratch register when they are expanded to long branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158432 91177308-0d34-0410-b5e6-96231b3b80d8
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to load an immediate that does not fit into 16-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158431 91177308-0d34-0410-b5e6-96231b3b80d8
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to load an immediate that does not fit into 16-bit. Also, take into
consideration the global base register slot on the stack when computing the
stack size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158430 91177308-0d34-0410-b5e6-96231b3b80d8
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compute the size of basic blocks in a function. Also, define a function which
emits a series of instructions to load an immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158429 91177308-0d34-0410-b5e6-96231b3b80d8
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Long-branches need access to the global base register to get the destination
address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158428 91177308-0d34-0410-b5e6-96231b3b80d8
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object for the global base register.
This is the first of a series of patches which implements long branch expansion
for MIPS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158427 91177308-0d34-0410-b5e6-96231b3b80d8
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delay slot filler pass of MIPS, per suggestion of Jakob Stoklund Olesen.
This change, along with the fix in r158154, enables machine verification
to be run after delay slot filling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158426 91177308-0d34-0410-b5e6-96231b3b80d8
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pattern:
(add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
"tjt" is a TargetJumpTable node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158419 91177308-0d34-0410-b5e6-96231b3b80d8
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Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158382 91177308-0d34-0410-b5e6-96231b3b80d8
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until this directive is pushed in gas to open source fsf
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158381 91177308-0d34-0410-b5e6-96231b3b80d8
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non mips16
2. fix some comments to change OPcode->EXTEND for extended instructions
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158378 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158250 91177308-0d34-0410-b5e6-96231b3b80d8
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inserted after the shift-left-logical node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157937 91177308-0d34-0410-b5e6-96231b3b80d8
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