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2010-11-14move all the target's asmprinters into the main target. The piece Chris Lattner
that should be split out is the InstPrinter (if a target is mc'ized). This change makes all the targets be consistent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119056 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com>Bruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118864 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10Add clo instruction. Patch by Akira Hatanaka (ahatanaka@mips.com) with some ↵Bruno Cardoso Lopes
minor tweaks git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118667 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Fix trailing whitespace and style, no functionality changeBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118515 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka ↵Bruno Cardoso Lopes
(ahatanaka@mips.com) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118447 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04In the calling convention logic, ValVT is always a legal type,Duncan Sands
and as such can be represented by an MVT - the more complicated EVT is not needed. Use MVT for ValVT everywhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118245 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03Inside the calling convention logic LocVT is always a simpleDuncan Sands
value type, so there is no point in passing it around using an EVT. Use the simpler MVT everywhere. Rather than trying to propagate this information maximally in all the code that using the calling convention stuff, I chose to do a mainly low impact change instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118167 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29Inline asm multiple alternative constraints development phase 2 - improved ↵John Thompson
basic logic, added initial platform support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117667 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28Add support to model pipeline bypass / forwarding.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115005 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28Removed a bunch of unnecessary target_link_libraries.Oscar Fuentes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114999 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28Remove trailing spaces of MipsMachineFunction.hChe-Liang Chiou
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114948 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28Remove trailing spaces of MipsTargetObjectFile.cppChe-Liang Chiou
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114947 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21fix a long standing wart: all the ComplexPattern's were beingChris Lattner
passed the root of the match, even though only a few patterns actually needed this (one in X86, several in ARM [which should be refactored anyway], and some in CellSPU that I don't feel like detangling). Instead of requiring all ComplexPatterns to take the dead root, have targets opt into getting the root by putting SDNPWantRoot on the ComplexPattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21eliminate some uses of the getStore overload.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21convert the targets off the non-MachinePointerInfo of getLoad.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114410 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03Remove Predicate_* calls from MipsJakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112919 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26Simplify eliminateFrameIndex() interface back down now that PEI doesn't needJim Grosbach
to try to re-use scavenged frame index reference registers. rdar://8277890 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112241 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18Don't call Predicate_* in Mips.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111468 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17fix emacs language spec's, patch by Edmund Grimley-Evans!Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111241 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06Revert r110396 to fix buildbots.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110410 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson
address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110396 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20Fix PR7174, a couple o Mips fixes:Bruno Cardoso Lopes
- Fix a typo for PIC check during jmp table lowering - Also fix the "first jump table basic block is not considered only reachable by fall through" problem, use this ad-hoc solution until I come up with something better. Patch by stetorvs@gmail.com git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108820 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20Fix Mips PR7473. Patch by stetorvs@gmail.comBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108816 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16Remove the isMoveInstr() hook.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14Don't pass StringRef by reference.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108366 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11RISC architectures get their memory operand folding for free.Jakob Stoklund Olesen
The only folding these load/store architectures can do is converting COPY into a load or store, and the target independent part of foldMemoryOperand already knows how to do that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108099 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11Replace copyRegToReg with copyPhysReg for Mips.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108066 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10Use COPY in targetsJakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108063 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07Split the SDValue out of OutputArg so that SelectionDAG-independentDan Gohman
code can do calling-convention queries. This obviates OutputArgReg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107786 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06Propagate debug loc.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06Reapply r107655 with fixes; insert the pseudo instruction intoDan Gohman
the block before calling the expansion hook. And don't put EFLAGS in a mbb's live-in list twice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107691 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06Revert r107655.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107668 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06Fix a bunch of custom-inserter functions to handle the case whereDan Gohman
the pseudo instruction is not at the end of the block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107655 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill ↵Evan Cheng
slots so it's always false. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107550 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21Remove isTwoAddress from Mips.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106465 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). ThisStuart Hastings
addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02Remove the TargetRegisterClass member from CalleeSavedInfoRafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105344 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02cleanupRafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105322 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen
A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."Jakob Stoklund Olesen
This reverts commit 104654. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen
A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25Remove NumberHack entirely.Jakob Stoklund Olesen
SubRegIndex instances are now numbered uniquely the same way Register instances are - in lexicographical order by name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104627 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24Switch SubRegSet to using symbolic SubRegIndicesJakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24Replace the tablegen RegisterClass field SubRegClassList with an alist-like dataJakob Stoklund Olesen
structure that represents a mapping without any dependencies on SubRegIndex numbering. This brings us closer to being able to remove the explicit SubRegIndex numbering, and it is now possible to specify any mapping without inventing *_INVALID register classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24SubRegIndex'ize MipsJakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104514 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe whatBill Wendling
the variable actually tracks. N.B., several back-ends are using "HasCalls" as being synonymous for something that adjusts the stack. This isn't 100% correct and should be looked into. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103802 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11Implement a bunch more TargetSelectionDAGInfo infrastructure.Dan Gohman
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and EmitTargetCodeForMemmove out of TargetLowering and into SelectionDAGInfo to exercise this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman
doesn't have to guess. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
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