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2012-10-10Implement MipsTargetLowering::CanLowerReturn.Akira Hatanaka
Patch by Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165585 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09Initial assembler implementation of Mips load address macroJack Carter
This patch provides initial implementation of load address macro instruction for Mips. We have implemented two kinds of expansions with their variations depending on the size of immediate operand: 1) load address with immediate value directly: * la d,j => addiu d,$zero,j (for -32768 <= j <= 65535) * la d,j => lui d,hi16(j) ori d,d,lo16(j) (for any other 32 bit value of j) 2) load load address with register offset value * la d,j(s) => addiu d,s,j (for -32768 <= j <= 65535) * la d,j(s) => lui d,hi16(j) (for any other 32 bit value of j) ori d,d,lo16(j) addu d,d,s This patch does not cover the case when the address is loaded from the value of the label or function. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165561 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09Improvements to MIPS64 assembler:David Chisnall
- Teach it about dadd[i] instructions and move pseudo-instruction - Make it parse the register names correctly (for N32 / N64) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165506 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08Move TargetData to DataLayout.Micah Villmow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165402 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-06Adding support for instructions mfc0, mfc2, mtc0, mtc2Jack Carter
move from and to coprocessors 0 and 2. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165351 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-06Minor changes based on post commit review:Jack Carter
Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165350 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-05Minor changes based on post commit review:Jack Carter
Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165346 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-05[ms-inline asm] Add a few typedefs to simplify future changes.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165324 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-05Patch for integer multiply, signed/unsigned, long/long long.Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165322 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04Implement methods that enable expansion of load immediate Jack Carter
macro instruction (li) in the assembler. We have identified three possible expansions depending on the size of immediate operand: 1) for 0 ≤ j ≤ 65535. li d,j => ori d,$zero,j 2) for −32768 ≤ j < 0. li d,j => addiu d,$zero,j 3) for any other value of j that is representable as a 32-bit integer. li d,j => lui d,hi16(j) ori d,d,lo16(j) All of the above have been implemented in ths patch. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165199 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04This patch is a partial implementation of mips .set assembler directive. ↵Jack Carter
Directive is defined as follows: .set option The patch implements following options at - lets the assembler use the $at register for macros, but generates warnings if the source program uses $at noat - let source programs use $at without issuingwarnings. noreorder - prevents the assembler from reordering machine language instructions. nomacro - causes the assembler to print a warning whenever an assembler operation generates more than one machine language instruction. macro - lets the assembler generate multiple machine instructions from a single assembler instruction reorder - lets the assembler reorder machine language instructions to improve performance The above variants are parsed and their boolean values set or unset. The code to actually use them will come later. Following options are not implemented yet: nomips16 nomicromips move nomove Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165194 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03This patch moves from using a hard coded number (4) Jack Carter
for the number of bytes in a particular instruction to using const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode()); Desc.getSize() This is necessary with the advent of 16 bit instructions with mips16 and micromips. It is also puts Mips in compliance with the other targets for getting instruction size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165171 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02The mips 64bit instructions DSLL, DSRA, DSRL, DEXT and DINS get transformed ↵Jack Carter
by the assembler or through codegen direct object output to other variants based on the value of the immediate values of the operands. If the code is generated as assembler, this transformation does not occur assuming that it will occur later in the assembler. This code was originally called from MipsAsmPrinter.cpp and we needed to check for OutStreamer.hasRawTextSupport(). This was not a good place for it and has been moved to MCTargetDesc/MipsMCCodeEmitter.cpp where both direct object and the assembler use it it automagically. The test cases have been checked in for a number of weeks now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165067 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-01[ms-inline asm] Add the convertToMapAndConstraints() function that is used toChad Rosier
map constraints and MCInst operands to inline asm operands. This replaces the getMCInstOperandNum() function. The logic to determine the constraints are not in place, so we still default to a register constraint (i.e., "r"). Also, we no longer build the MCInst but rather return just the opcode to get the MCInstrDesc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164979 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-28MIPS DSP: other miscellaneous instructions.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164845 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-28MIPS DSP: ADDUH.QB instruction sub-class.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164840 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-281. Add load/store words from the stackReed Kotler
2. As part of this, added assembly format FEXT_RI16_SP_explicit_ins and moved other lines for FEXT_RI16 formats to be in the right place in the code. 3. Added mayLoad and mayStore assignements for the load/store instructions added and for ones already there that did not have this assignment. 4. Another patch will deal with the problem of load/store byte/halfword to the stack. This is a particular Mips16 problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164811 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: ABSQ_S.PH instruction sub-class.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164787 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: SHLL.QB instruction sub-class.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164786 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: rddsp (instruction which reads DSPControl register fields to a GPR).Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164756 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: CMPU.EQ.QB instruction sub-class.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164755 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: ADDU.QB instruction sub-class.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164754 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: Branch on Greater Than or Equal To Value 32 in DSPControl Pos ↵Akira Hatanaka
Field instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164751 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: all the remaining instructions which read or write accumulators.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164750 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: add support for extract-word instructions.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164749 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: add functions which decode DSP and accumulator registers.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164748 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: add code necessary for pseudo instruction lowering.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164747 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: add bitcast patterns between vectors and int.Akira Hatanaka
No test cases. These patterns will get tested along with dsp intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164746 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: add vector load/store patterns.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164744 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26Add case clauses for returning dsp accumulator encoding values in functionAkira Hatanaka
getMipsRegisterNumbering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164720 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26Add DSP accumulator registers and register class. Remove hi/lo registers.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164719 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26Delete member MipsFunctionInfo::OutArgFIRange and code that accesses it.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164718 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25Initialize boolean variables in MipsSubtarget's constructor.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164642 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25blank line for test commitReed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164640 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Rather then have a wrapper function, have tblgen instantiate the implementation.Chad Rosier
Also remove an unused argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164567 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Rather then have a wrapper function, have tblgen instantiate the implementation.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164548 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-22MIPS DSP: Add immediate leaves.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164435 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-22MIPS DSP: Add predicates and instruction template.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164434 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Add MIPS DSP register classes. Set actions of DSP vector operations and overrideAkira Hatanaka
TargetLowering's callback functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164431 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21SelectionDAG node enums for MIPS DSP nodes.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164430 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Add MIPS accumulator and DSP control registers.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164429 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Add flags and feature bits for mips dsp.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164428 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21[ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164420 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Mips16FrameLowering.cpp: Remove unused TII introduced in r164349. ↵NAKAMURA Takumi
[-Wunused-variable] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164354 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Properly save and restore RA and Mips16 callee save registers S0,S1Akira Hatanaka
Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164349 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18Revert r164051.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164150 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18When creating MCAsmBackend pass the CPU string as well. In X86AsmBackendRoman Divacky
store this and use it to not emit long nops when the CPU is geode which doesnt support them. Fixes PR11212. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164132 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17Make sure there is enough room for RA. getStackSize needs to be cleaned up butAkira Hatanaka
we will do that when we implement the full save/restore. Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164051 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-15Remove unused private fields to silence -Wunused-private-field.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163973 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-15Remove aligned/unaligned load/store fragments defined in MipsInstrInfo.td andAkira Hatanaka
use load/store fragments defined in TargetSelectionDAG.td in place of them. Unaligned loads/stores are either expanded or lowered to target-specific nodes, so instruction selection should see only aligned load/store nodes. No changes in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163960 91177308-0d34-0410-b5e6-96231b3b80d8
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