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path: root/lib/Target/Mips/MipsRegisterInfo.cpp
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2013-01-31[PEI] Pass the frame index operand number to the eliminateFrameIndex function.Chad Rosier
Each target implementation was needlessly recomputing the index. Part of rdar://13076458 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22[mips] Implement MipsRegisterInfo::getRegPressureLimit.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173197 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-02Move all of the header files which are involved in modelling the LLVM IRChandler Carruth
into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03Use the new script to sort the includes of every file under lib.Chandler Carruth
Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-03[mips] Stop reserving register AT and use register scavenger when a scratchAkira Hatanaka
register is needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167341 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-02[mips] Do not reserve all 64-bit registers, but only the ones which need to beAkira Hatanaka
reserved. Without this fix, RegScavenger::getRegsAvailable incorrectly returns an empty set of integer registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167335 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-28This patch is for the implementation of mips16 complex pattern addr16.Reed Kotler
Previously mips16 was sharing the pattern addr which is used for mips32 and mips64. This had a number of problems: 1) Storing and loading byte and halfword quantities for mips16 has particular problems due to the primarily non mips16 nature of SP. When we must load/store byte/halfword stack objects in a function, we must create a mips16 alias register for SP. This functionality is tested in stchar.ll. 2) We need to have an FP register under certain conditions (such as dynamically sized alloca). We use mips16 register S0 for this purpose. In this case, we also use this register when accessing frame objects so this issue also affects the complex pattern addr16. This functionality is tested in alloca16.ll. The Mips16InstrInfo.td has been updated to use addr16 instead of addr. The complex pattern C++ function for addr has been copied to addr16 and updated to reflect the above issues. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166897 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Add MIPS accumulator and DSP control registers.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164429 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-22Add a member of type Mips16InstrInfo/MipsSEInstrInfo to classAkira Hatanaka
Mips16RegisterInfo/MipsSERegisterInfo. No changes in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162413 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-22Add a getName function to MachineFunction. Use it in places that previously ↵Craig Topper
did getFunction()->getName(). Remove includes of Function.h that are no longer needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162347 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-22Add register Mips::GP to the list of reserved registers if target is bare-metalAkira Hatanaka
to prevent it from being clobbered. mips uses $gp to access small data section. This bug was originally reported by Carl Norum. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162340 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31Implement MipsSERegisterInfo::eliminateCallFramePseudoInstr. The function emitsAkira Hatanaka
instructions that decrement and increment the stack pointer before and after a call when the function does not have a reserved call frame. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161093 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31Add definitions of two subclasses of MipsRegisterInfo, Mips16RegisterInfo andAkira Hatanaka
MipsSERegisterInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161092 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31Expand DYNAMIC_STACKALLOC nodes rather than doing custom-lowering.Akira Hatanaka
The frame object which points to the dynamically allocated area will not be needed after changes are made to cease reserving call frames. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161076 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-25Eliminate the stack slot used to save the global base register.Akira Hatanaka
The long branch pass (fixed in r160601) no longer uses the global base register to compute addresses of branch destinations, so it is not necessary to reserve a slot on the stack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160703 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Make register Mips::RA allocatable if not in mips16 mode.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159971 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-28Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp andBill Wendling
include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h. The reasoning is because the DebugInfo module is simply an interface to the debug info MDNodes and has nothing to do with analysis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159312 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-14Fix coding style violations. Remove white spaces and tabs.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158471 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-14In MipsRegisterInfo::eliminateFrameIndex, call Mips::loadImmediateAkira Hatanaka
to load an immediate that does not fit into 16-bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158431 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-12Stop reserving register $gp. Do not call isGPFI to check whether a frame objectAkira Hatanaka
is the $gp save slot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156694 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11Fix a misleading comment.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156603 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09Make register FP allocatable if the compiled function does not have dynamicAkira Hatanaka
allocas. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156458 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23This patch fixes a problem which arose when using the Post-RA schedulerPreston Gurd
on X86 Atom. Some of our tests failed because the tail merging part of the BranchFolding pass was creating new basic blocks which did not contain live-in information. When the anti-dependency code in the Post-RA scheduler ran, it would sometimes rename the register containing the function return value because the fact that the return value was live-in to the subsequent block had been lost. To fix this, it is necessary to run the RegisterScavenging code in the BranchFolding pass. This patch makes sure that the register scavenging code is invoked in the X86 subtarget only when post-RA scheduling is being done. Post RA scheduling in the X86 subtarget is only done for Atom. This patch adds a new function to the TargetRegisterClass to control whether or not live-ins should be preserved during branch folding. This is necessary in order for the anti-dependency optimizations done during the PostRASchedulerList pass to work properly when doing Post-RA scheduling for the X86 in general and for the Intel Atom in particular. The patch adds and invokes the new function trackLivenessAfterRegAlloc() instead of using the existing requiresRegisterScavenging(). It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of requiresRegisterScavenging(). It changes the all the targets that implemented requiresRegisterScavenging() to also implement trackLivenessAfterRegAlloc(). It adds an assertion in the Post RA scheduler to make sure that post RA liveness information is available when it is needed. It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order to avoid running into the added assertion. Finally, this patch restores the use of anti-dependency checking (which was turned off temporarily for the 3.1 release) for Intel Atom in the Post RA scheduler. Patch by Andy Zhang! Thanks to Jakob and Anton for their reviews. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155395 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper
since they are equivalent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Turn on post register allocation scheduler.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153554 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Emit all directives except for ".cprestore" during asm printing rather than emitAkira Hatanaka
them as machine instructions. Directives ".set noat" and ".set at" are now emitted only at the beginning and end of a function except in the case where they are emitted to enclose .cpload with an immediate operand that doesn't fit in 16-bit field or unaligned load/stores. Also, make the following changes: - Remove function isUnalignedLoadStore and use a switch-case statement to determine whether an instruction is an unaligned load or store. - Define helper function CreateMCInst which generates an instance of an MCInst from an opcode and a list of operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153552 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27Remove trailing white space.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153536 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27Reserve hardware registers.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153486 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper
some superfluous forward declarations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-11Use uint16_t to store registers and opcode in static tables in the target ↵Craig Topper
specific backends. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152537 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper
size of static data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Changes for migrating to using register mask operands.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151847 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28remove blanks, and some code formatJia Liu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151625 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24Add an option to use a virtual register as the global base register instead ofAkira Hatanaka
reserving a physical register ($gp or $28) for that purpose. This will completely eliminate loads that restore the value of $gp after every function call, if the register allocator assigns a callee-saved register, or eliminate unnecessary loads if it assigns a temporary register. example: .cpload $25 // set $gp. ... .cprestore 16 // store $gp to stack slot 16($sp). ... jalr $25 // function call. clobbers $gp. lw $gp, 16($sp) // not emitted if callee-saved reg is chosen. ... lw $2, 4($gp) ... jalr $25 // function call. lw $gp, 16($sp) // not emitted if $gp is not live after this instruction. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151402 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.Jia Liu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150805 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25Modify MipsRegisterInfo::eliminateFrameIndex to use MipsAnalyzeImmediate toAkira Hatanaka
expand offsets that do not fit in the 16-bit immediate field of load and store instructions. Also change the types of variables so that they are sufficiently large to handle 64-bit pointers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148916 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20More dead code removal (using -Wunreachable-code)David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-30Cleanup Mips code and rename some variables. Patch by Jack CarterBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147383 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06Add register HWR29 numbering. Patch by Jack CarterBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145910 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15Fix functions in MipsFrameLowering.cpp and MipsRegisterInfo.cpp. Use 64-bitAkira Hatanaka
registers and instructions when ABI is N64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144666 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-07Use array_lengthof to compute the number of iterations of a loop.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143991 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27Fix function MipsRegisterInfo::getRegisterNumbering.Akira Hatanaka
Return numbers of 64-bit registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140609 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23Add definitions of 64-bit register files. Add code for returning Mips64's ↵Akira Hatanaka
sets of callee-saved registers and reserved registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140395 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-22Add F31 to the set of callee-saved registers.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140315 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Make F31 and D15 non-reserved registers.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139420 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Mips32 does not reserve even-numbered floating point registers.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139412 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions forEvan Cheng
better location welcome). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135438 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng
to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng
registeration and creation code into XXXMCDesc libraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07Simplify MipsRegisterInfo::eliminateFrameIndex.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134628 91177308-0d34-0410-b5e6-96231b3b80d8
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