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path: root/lib/Target/MBlaze/MBlazeTargetMachine.cpp
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2012-10-28Remove TargetELFWriterInfo.Rafael Espindola
All the credit goes to Jan Voung for noticing it was dead! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24Implement a basic VectorTargetTransformInfo interface to be used by the loop ↵Nadav Rotem
and bb vectorizers for modeling the cost of instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166593 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-18Reapply the TargerTransformInfo changes, minus the changes to LSR and ↵Nadav Rotem
Lowerinvoke. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166248 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-18Temporarily revert the TargetTransform changes.Bob Wilson
The TargetTransform changes are breaking LTO bootstraps of clang. I am working with Nadav to figure out the problem, but I am reverting it for now to get our buildbots working. This reverts svn commits: 165665 165669 165670 165786 165787 165997 and I have also reverted clang svn 165741 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166168 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Add a new interface to allow IR-level passes to access codegen-specific ↵Nadav Rotem
information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165665 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08Move TargetData to DataLayout.Micah Villmow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165402 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Add all codegen passes to the PassManager via TargetPassConfig.Bob Wilson
This is a preliminary step toward having TargetPassConfig be able to start and stop the compilation at specified passes for unit testing and debugging. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159567 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01Change the PassManager from a reference to a pointer.Bill Wendling
The TargetPassManager's default constructor wants to initialize the PassManager to 'null'. But it's illegal to bind a null reference to a null l-value. Make the ivar a pointer instead. PR12468 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper
some superfluous forward declarations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-04TargetPassConfig: confine the MC configuration to TargetMachine.Andrew Trick
Passes prior to instructon selection are now split into separate configurable stages. Header dependencies are simplified. The bulk of this diff is simply removal of the silly DisableVerify flags. Sorry for the target header churn. Attempting to stabilize them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149754 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03Added TargetPassConfig. The first little step toward configuring codegen passes.Andrew Trick
Allows command line overrides to be centralized in LLVMTargetMachine.cpp. LLVMTargetMachine can intercept common passes and give precedence to command line overrides. Allows adding "internal" target configuration options without touching TargetOptions. Encapsulates the PassManager. Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs. Allows modifying the target configuration hooks without rebuilding the world. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149672 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky
change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16Sink codegen optimization level into MCCodeGenInfo along side relocation modelEvan Cheng
and code model. This eliminates the need to pass OptLevel flag all over the place and makes it possible for any codegen pass to use this information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144788 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng
These are strictly utilities for registering targets and components. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25Refactor MBlaze target to separate MC routines from Target routines.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135953 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20- Move CodeModel from a TargetMachine global option to MCCodeGenInfo.Evan Cheng
- Introduce JITDefault code model. This tells targets to set different default code model for JIT. This eliminates the ugly hack in TargetMachine where code model is changed after construction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135580 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19Introduce MCCodeGenInfo, which keeps information that can affect codegenEvan Cheng
(including compilation, assembly). Move relocation model Reloc::Model from TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135468 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14Rename createAsmInfo to createMCAsmInfo and move registration code to ↵Evan Cheng
MCTargetDesc to prepare for next round of changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135219 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08Eliminate asm parser's dependency on TargetMachine:Evan Cheng
- Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134678 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng
be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134127 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19ADT/Triple: Move a variety of clients to using isOSDarwin() and isOSWindows()Daniel Dunbar
predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129816 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11Add scheduling information for the MBlaze backend.Wesley Peck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129311 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-17Triple::MinGW64 is deprecated and removed. We can use Triple::MinGW32 generally.NAKAMURA Takumi
No one uses *-mingw64. mingw-w64 is represented as {i686|x86_64}-w64-mingw32. In llvm side, i686 and x64 can be treated as similar way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125747 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-23Add support for the --noexecstack option.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124077 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-10Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov
and fixes here and there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09Reworking the stack layout generated by the MBlaze backend.Wesley Peck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121355 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-241. Fixing error where basic block labels were not being printed out when ↵Wesley Peck
they need to be for the MBlaze backend because AsmPrinter::isBlockOnlyReachableByFallthrough does not take into account delay slots. 2. Re-adding .mask and .frame directives in printed assembly. 3. Adding .ent and .end directives in printed assembly. 4. Minor cleanups to MBlaze backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120095 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15First step of huge frame-related refactoring: move emit{Prologue,Epilogue} ↵Anton Korobeynikov
out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119097 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08Adding working version of assembly parser for the MBlaze backendWesley Peck
Major cleanup of whitespace and formatting issues in MBlaze backend git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118434 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Adding disassembler to the MicroBlaze backend.Wesley Peck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117420 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21Adding initial AsmParser implementation for the MBlaze backend. It isWesley Peck
mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117054 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21Recommit 116986 with capitalization typo fixed.Wesley Peck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116993 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21Reverting the commit 116986. It was breaking the build on llvm-x86_64-linux ↵Wesley Peck
though it compiles on OS X. I'll ensure that it builds on a linux machine before committing again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-21Major update of the MicroBlaze backend. The new features are:Wesley Peck
1. A delay slot filler that searches for valid instructions to fill the delay slot with. Previously NOPs would always be inserted into delay slots. 2. Support for MC based instruction printer added. 3. Support for MC based machine code generation and ELF file generation. ELF file generation does not yet completely work as much of the ELF support infrastructure is still x86/x86-64 specific. 4. General clean up of the MBlaze backend code. Much of the tablegen code has been cleanup and simplified. Bug Fixes: 1. Removed duplicate periods from subtarget feature descriptions. 2. Many of the instructions had bad machine code information in the tablegen files. Much of this has been fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116986 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11Implement a bunch more TargetSelectionDAGInfo infrastructure.Dan Gohman
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and EmitTargetCodeForMemmove out of TargetLowering and into SelectionDAGInfo to exercise this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-23Adding the MicroBlaze backend.Wesley Peck
The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96969 91177308-0d34-0410-b5e6-96231b3b80d8
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