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2012-01-26Add support for the R_ARM_TARGET1 relocation, which should be given to ↵James Molloy
relocations applied to all C++ constructors and destructors. This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149057 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25Properly emit ctors / dtors with priorities into desired sectionsAnton Korobeynikov
and let linker handle the rest. This finally fixes PR5329 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148990 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25ARM assemly parsing and validation of IT instruction.Jim Grosbach
"Although a Thumb2 instruction, the IT mnemonic shall be permitted in ARM mode, and the condition verified to match the condition code(s) on the following instruction(s)." PR11853 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148969 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25NEON VLD4(all lanes) assembly parsing and encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148884 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Tidy up. Rename VLD4DUP patterns for consistency.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148883 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24NEON VLD3(all lanes) assembly parsing and encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148882 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24NEON VST4(one lane) assembly parsing and encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148836 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Widen the instruction encoder that TblGen emits to a 64 bits, which should ↵Owen Anderson
accomodate every target I can think of offhand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148833 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24NEON VLD4(one lane) assembly parsing and encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148832 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24NEON Two-operand assembly aliases for VSRA.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148821 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24NEON Two-operand assembly aliases for VSLI.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148819 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24NEON Two-operand assembly aliases for VSRI.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148818 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24NEON add correct predicates for some asm aliases.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148815 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Use correct register class for am2offset register operands.Anton Korobeynikov
This pacifies machine verifier git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148782 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24NEON VST4(multiple 4 element structures) assembly parsing.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148764 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24NEON VLD4(multiple 4 element structures) assembly parsing.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148762 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Tidy up. Remove some vertical space for readability.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148761 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Revert r148686 (and r148694, a fix to it) due to a serious layeringChandler Carruth
violation -- MC cannot depend on CodeGen. Specifically, the MCTargetDesc component of each target is actually a subcomponent of the MC library. As such, it cannot depend on the target-independent code generator, because MC itself cannot depend on the target-independent code generator. This change moved a flag from the ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in ARMException.cpp, leaving behind an 'extern' to refer back to it. That layering order isn't viable givin the constraints outlined above. Commandline flags are designed to be static specifically to avoid these types of bugs. Fixing this is likely going to require some non-trivial refactoring. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148759 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Fix typo.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148757 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24NEON VST3(single element from one lane) assembly parsing.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148755 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23NEON VST3(multiple 3-element structures) assembly parsing.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148748 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23NEON VLD3(multiple 3-element structures) assembly parsing.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148745 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23Add missed mayStore flag to STREXD / t2STREXDAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148742 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23NEON VLD3 lane-indexed assembly parsing and encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148734 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23Simplify some NEON assembly pseudo definitions.Jim Grosbach
Let the generic token alias definitions handle the data subtype suffices. We don't need explicit versions for each. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148718 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23ARMAsmPrinter.cpp: Try to fix up r148686. EnableARMEHABI was also here.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148694 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23An option to selectively enable parts of ARM EHABI support.Evgeniy Stepanov
This change adds an new value to the --arm-enable-ehabi option that disables emitting unwinding descriptors. This mode gives a working backtrace() without the (currently broken) exception support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148686 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-22Add fused multiple+add instructions from VFPv4.Anton Korobeynikov
Patch by Ana Pazos! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148658 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-21Thumb2 'add rd, pc, imm' alternate form for 'adr' instruction.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148601 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20More dead code removal (using -Wunreachable-code)David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651>Bob Wilson
We have patterns for vector sext and zext operations but were missing anyext. Without those patterns, codegen will fail when the selection DAG has any_extend nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148568 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20VST2 four-register w/ update pseudos for fixed/register update.Jim Grosbach
rdar://10724489 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148560 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20NEON use vmov.i32 to splat some f32 values into vectors.Jim Grosbach
For bit patterns that aren't representable using the 8-bit floating point representation for vmov.f32, but are representable via vmov.i32, treat the .f32 syntax as an alias. Most importantly, this covers the case 'vmov.f32 Vd, #0.0'. rdar://10616677 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19Silence warnings about mixing enums.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148495 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19Emit ARM EHABI unwinding instructions for 3 more Thumb instructions.Evgeniy Stepanov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148473 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19ARM assembly diagnostic caret in better position for FPImm.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148459 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19Thumb2 relaxation for tADR to t2ADR.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148456 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19Add comment and fix range check in condition.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148455 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19- Slight change to finalizeBundle() interface. LastMI is not exclusive (pointingEvan Cheng
to instruction right after the last instruction in the bundle. - Add a finalizeBundle() variant that doesn't specify LastMI. Instead, the code will find the last instruction in the bundle by following the 'InsideBundle' marker. This is useful in case bundles are formed early (i.e. during MI scheduling) but finalized later (i.e. after register allocator has finished rewriting virtual registers with physical registers). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148444 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19Rename Finalizebundle to finalizeBundle to conform to coding guideline.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148440 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Ignore register mask operands when lowering instructions to MC.Jakob Stoklund Olesen
This is similar to implicit register operands. MC doesn't understand register liveness and call clobbers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148437 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Thumb2 alternate syntax for LDR(literal) and friends.Jim Grosbach
Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]". rdar://10250964 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148432 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Replace FIXME with explanatory comment.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148427 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Thumb2 relaxation for LDR(literal).Jim Grosbach
If the fixup is out of range for the Thumb1 instruction, relax it to the Thumb2 encoding instead. rdar://10711829 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148424 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Rename pattern for clarity.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148422 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Tidy up. MCAsmBackend naming conventions.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148400 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Thumb2 load/store fixups don't set the thumb bit.Jim Grosbach
Load/store instructions w/ a fixup to be relative a function marked as thumb don't use the low bit to specify thumb vs. non-thumb like interworking branches do, so don't set it when dealing with those fixups. rdar://10348687. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148366 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Move some ARM specific MCAssmebler bits into the ARMAsmBackend.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148364 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Add a CoveredBySubRegs property to Register descriptions.Jakob Stoklund Olesen
When set, this bit indicates that a register is completely defined by the value of its sub-registers. Use the CoveredBySubRegs property to infer which super-registers are call-preserved given a list of callee-saved registers. For example, the ARM registers D8-D15 are callee-saved. This now automatically implies that Q4-Q7 are call-preserved. Conversely, Win64 callees save XMM6-XMM15, but the corresponding YMM6-YMM15 registers are not call-preserved because they are not fully defined by their sub-registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148363 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17Implement ARMBaseRegisterInfo::getCallPreservedMask().Jakob Stoklund Olesen
Move ARM callee-saved lists into ARMCallingConv.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148357 91177308-0d34-0410-b5e6-96231b3b80d8
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