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2012-07-06Revert r159804, "[arm-fast-isel] Add support for vararg function calls."NAKAMURA Takumi
It broke LLVM :: CodeGen/Thumb2/large-call.ll on several hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159817 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06[arm-fast-isel] Add support for vararg function calls.Jush Lu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159804 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Consistently use AnalysisID types in TargetPassConfig.Bob Wilson
This makes it possible to just use a zero value to represent "no pass", so the phony NoPassID global variable is no longer needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159568 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Add all codegen passes to the PassManager via TargetPassConfig.Bob Wilson
This is a preliminary step toward having TargetPassConfig be able to start and stop the compilation at specified passes for unit testing and debugging. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159567 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Revert accidental checkin.Andrew Trick
My last checkin was apparently not the branch I intended. It was missing one change (added by chandlerc), and contained a spurious change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159548 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick
Reapplies r159406 with minor cleanup. The regressions appear to have been spurious. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159541 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Do not attempt to use ROR for Thumb1.Bob Wilson
Patch by Matt Fischer! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159538 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29ARM: Clean up optimizeCompare in peephole, no functional change.Manman Ren
Use getUniqueVRegDef. Replace a loop with existing interfaces: modifiesRegister and readsRegister. Factor out code into inline functions and simplify the code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159470 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29Add SrcReg2 to analyzeCompare and optimizeCompareInstr to handle CompareManman Ren
instructions with two register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159465 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick
This reverts commit r159406. I noticed a performance regression so I'll back out for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159411 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29Make NumMicroOps a variable in the subtarget's instruction itinerary.Andrew Trick
The TargetInstrInfo::getNumMicroOps API does not change, but soon it will be used by MachineScheduler. Now each subtarget can specify the number of micro-ops per itinerary class. For ARM, this is currently always dynamic (-1), because it is used for load/store multiple which depends on the number of register operands. Zero is now a valid number of micro-ops. This can be used for nop pseudo-instructions or instructions that the hardware can squash during dispatch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159406 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-28Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp andBill Wendling
include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h. The reasoning is because the DebugInfo module is simply an interface to the debug info MDNodes and has nothing to do with analysis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159312 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-27Teach assembler to handle capitalised operation values for DSB instructionsRichard Barton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159259 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-27Prevent ARM Assembler crashing on unrecognised assembly format for DSB ↵Richard Barton
instruction git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159257 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-26Add a missing check to avoid dereference null. No sensible test case ↵Evan Cheng
possible. Sorry. rdar://11745134 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159236 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-26There are a number of generic inline asm operand modifiers thatJack Carter
up to r158925 were handled as processor specific. Making them generic and putting tests for these modifiers in the CodeGen/Generic directory caused a number of targets to fail. This commit addresses that problem by having the targets call the generic routine for generic modifiers that they don't currently have explicit code for. For now only generic print operands 'c' and 'n' are supported.vi Affected files: test/CodeGen/Generic/asm-large-immediate.ll lib/Target/PowerPC/PPCAsmPrinter.cpp lib/Target/NVPTX/NVPTXAsmPrinter.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/XCore/XCoreAsmPrinter.cpp lib/Target/X86/X86AsmPrinter.cpp lib/Target/Hexagon/HexagonAsmPrinter.cpp lib/Target/CellSPU/SPUAsmPrinter.cpp lib/Target/Sparc/SparcAsmPrinter.cpp lib/Target/MBlaze/MBlazeAsmPrinter.cpp lib/Target/Mips/MipsAsmPrinter.cpp MSP430 isn't represented because it did not even run with the long existing 'c' modifier and it was not apparent what needs to be done to get it inline asm ready. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159203 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-25ARM: update peephole optimization.Manman Ren
More condition codes are included when deciding whether to remove cmp after a sub instruction. Specifically, we extend from GE|LT|GT|LE to GE|LT|GT|LE|HS|LS|HI|LO|EQ|NE. If we have "sub a, b; cmp b, a; movhs", we should be able to replace with "sub a, b; movls". rdar: 11725965 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159166 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-24llvm/lib: [CMake] Add explicit dependency to intrinsics_gen.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159112 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23(sub X, imm) gets canonicalized to (add X, -imm)Evan Cheng
There are patterns to handle immediates when they fit in the immediate field. e.g. %sub = add i32 %x, -123 => sub r0, r0, #123 Add patterns to catch immediates that do not fit but should be materialized with a single movw instruction rather than movw + movt pair. e.g. %sub = add i32 %x, -65535 => movw r1, #65535 sub r0, r0, r1 rdar://11726136 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159057 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22ARM: Add a better diagnostic for some out of range immediates.Jim Grosbach
As an example of how the custom DiagnosticType can be used to provide better operand-mismatch diagnostics, add a custom diagnostic for the imm0_15 operand class used for several system instructions. Update the tests to expect the improved diagnostic. rdar://8987109 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159051 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22Use "NoItineraries" for processors with no itineraries.Andrew Trick
This makes it explicit when ScoreboardHazardRecognizer will be used. "GenericItineraries" would only make sense if it contained real itinerary values and still required ScoreboardHazardRecognizer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158963 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22ARM scheduling fix: don't guess at implicit operand latency.Andrew Trick
This is a minor drive-by fix with no robust way to unit test. As an example see neon-div.ll: SU(16): %Q8<def> = VMOVLsv4i32 %D17, pred:14, pred:%noreg, %Q8<imp-use,kill> val SU(1): Latency=2 Reg=%Q8 ...should be latency=1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158960 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22ARM scheduling fix: compute predicated implicit use properly.Andrew Trick
Minor drive by fix to cleanup latency computation. Calling getOperandLatency with a deliberately incorrect operand index does not give you the latency you want. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158959 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22Rename -allow-excess-fp-precision flag to -fuse-fp-ops, and switch from aLang Hames
boolean flag to an enum: { Fast, Standard, Strict } (default = Standard). This option controls the creation by optimizations of fused FP ops that store intermediate results in higher precision than IEEE allows (E.g. FMAs). The behavior of this option is intended to match the behaviour specified by a soon-to-be-introduced frontend flag: '-ffuse-fp-ops'. Fast mode - allows formation of fused FP ops whenever they're profitable. Standard mode - allow fusion only for 'blessed' FP ops. At present the only blessed op is the fmuladd intrinsic. In the future more blessed ops may be added. Strict mode - allow fusion only if/when it can be proven that the excess precision won't effect the result. Note: This option only controls formation of fused ops by the optimizers. Fused operations that are explicitly requested (e.g. FMA via the llvm.fma.* intrinsic) will always be honored, regardless of the value of this option. Internally TargetOptions::AllowExcessFPPrecision has been replaced by TargetOptions::AllowFPOpFusion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158956 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-21Add a missing llvm.fma -> VFNMS pattern to the ARM backend.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Add DAG-combines for aggressive FMA formation.Lang Hames
This patch adds DAG combines to form FMAs from pairs of FADD + FMUL or FSUB + FMUL. The combines are performed when: (a) Either AllowExcessFPPrecision option (-enable-excess-fp-precision for llc) OR UnsafeFPMath option (-enable-unsafe-fp-math) are set, and (b) TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) is true for the type of the FADD/FSUB, and (c) The FMUL only has one user (the FADD/FSUB). If your target has fast FMA instructions you can make use of these combines by overriding TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) to return true for types supported by your FMA instruction, and adding patterns to match ISD::FMA to your FMA instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158757 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Have ARM ELF use correct reloc for "b" instr.Jan Wen Voung
The condition code didn't actually matter for arm "b" instructions, unlike "bl". It should just use the R_ARM_JUMP24 reloc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158722 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Move the support for using .init_array from ARM to the genericRafael Espindola
TargetLoweringObjectFileELF. Use this to support it on X86. Unlike ARM, on X86 it is not easy to find out if .init_array should be used or not, so the decision is made via TargetOptions and defaults to off. Add a command line option to llc that enables it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158692 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-18ARM: use NOEN loads and stores if possible when handling struct byval.Manman Ren
This change is to be enabled in clang. rdar://9877866 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158684 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-18ARM: Define generic HINT instruction.Jim Grosbach
The NOP, WFE, WFI, SEV and YIELD instructions are all hints w/ a different immediate value in bits [7,0]. Define a generic HINT instruction and refactor NOP, WFI, WFI, SEV and YIELD to be assembly aliases of that. rdar://11600518 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158674 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-18This change handles a another case for generating the bic instruction Joel Jones
when a compile time constant is known. This occurs when implicitly zero extending function arguments from 16 bits to 32 bits. The 8 bit case doesn't need to be handled, as the 8 bit constants are encoded directly, thereby not needing a separate load instruction to form the constant into a register. <rdar://problem/11481151> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158659 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-15Fix the encoding of the armv7m (MClass) for MSR registers other than aspr,Kevin Enderby
iaspr, espr and xpsr which also needed to have 0b10 in their mask encoding bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158560 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-15ARM: optimization for sub+abs.Manman Ren
This patch will optimize abs(x-y) FROM sub, movs, rsbmi TO subs, rsbmi For abs, we will use cmp instead of movs. This is necessary because we already have an existing peephole pass which optimizes away cmp following sub. rdar: 11633193 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158551 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-15Preserve <undef> flags in ARMExpandPseudo.Jakob Stoklund Olesen
This probably mostly shows up in bugpoint-generated code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158527 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-14Replace assertion failure for badly formatted CPS instrution with error message.Richard Barton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158445 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-14Cleanup whitespace.Jush Lu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158443 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-12[arm-fast-isel] Add support for -arm-long-calls.Chad Rosier
Patch by Jush Lu <jush.msn@gmail.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158368 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-11Re-enable the CMN instruction.Bill Wendling
We turned off the CMN instruction because it had semantics which we weren't getting correct. If we are comparing with an immediate, then it's okay to use the CMN instruction. <rdar://problem/7569620> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158302 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07Continue factoring computeOperandLatency. Use it for ARM hasHighOperandLatency.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158164 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07ARM getOperandLatency rewrite.Andrew Trick
Match expectations of the new latency API. Cleanup and make the logic consistent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158163 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07ARM getOperandLatency should return -1 for unknown, consistent with APIAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158162 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07Fix ARM getInstrLatency logic to work with the current API.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158161 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Remove unused private fields found by clang's new -Wunused-private-field.Benjamin Kramer
There are some that I didn't remove this round because they looked like obvious stubs. There are dead variables in gtest too, they should be fixed upstream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158090 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Correct decoder for T1 conditional B encodingRichard Barton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158055 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05misched: API for minimum vs. expected latency.Andrew Trick
Minimum latency determines per-cycle scheduling groups. Expected latency determines critical path and cost. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158021 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05ARM itinerary properties.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157980 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05misched: Added MultiIssueItineraries.Andrew Trick
This allows a subtarget to explicitly specify the issue width and other properties without providing pipeline stage details for every instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157979 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05Revert commit r157966Joel Jones
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157972 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-04This change handles a another case for generating the bic instruction Joel Jones
when a compile time constant is known. This occurs when implicitly zero extending function arguments from 16 bits to 32 bits. <rdar://problem/11481151> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157966 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-02Fix typos found by http://github.com/lyda/misspell-checkBenjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157885 91177308-0d34-0410-b5e6-96231b3b80d8
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