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2011-11-16Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602>Bob Wilson
The EmitBasePointerRecalculation function has 2 problems, one minor and one fatal. The minor problem is that it inserts the code at the setjmp instead of in the dispatch block. The fatal problem is that at the point where this code runs, we don't know whether there will be a base pointer, so the entire function is a no-op. The base pointer recalculation needs to be handled as it was before, by inserting a pseudo instruction that gets expanded late. Most of the support for the old approach is still here, but it no longer has any connection to the eh_sjlj_dispatchsetup intrinsic. Clean up the parts related to the intrinsic and just generate the pseudo instruction directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144781 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16Add FIXME comment.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144743 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15Enable -widen-vmovs by default.Jakob Stoklund Olesen
This will widen 32-bit register vmov instructions to 64-bit when possible. The 64-bit vmovd instructions can then be translated to NEON vorr instructions by the execution dependency fix pass. The copies are only widened if they are marked as clobbering the whole D-register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144734 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15ARM assembly parsing for register range syntax for VLD/VST register lists.Jim Grosbach
For example, vld1.f64 {d2-d5}, [r2,:128]! Should be equivalent to: vld1.f64 {d2,d3,d4,d5}, [r2,:128]! It's not documented syntax in the ARM ARM, but it is consistent with what's accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to support. rdar://10451128 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144727 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15ARM assembly parsing for data type suffices on NEON VMOV aliases.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144722 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15ARM assembly parsing two operand forms for shift instructions.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144713 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15ARM VFP assembly parsing for VADD and VSUB two-operand forms.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144710 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15ARM accept an immediate offset in memory operands w/o the '#'.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144709 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15ARM enclosing curly braces optional on one-register VLD/VST instruction lists.Jim Grosbach
'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]' rdar://10450488. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144701 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15ARM size suffix on VFP single-precision 'vmov' is optional.Jim Grosbach
rdar://10435114 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144698 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15Fix typo.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144695 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15ARM alternate size suffices for VTRN instructions.Jim Grosbach
rdar://10435076 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144694 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15Fix a misplaced paren bug.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144692 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.Jim Grosbach
Yet more of rdar://10435076. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15ARM assembly parsing for two-operand form of 'mul' instruction.Jim Grosbach
rdar://10449856. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15ARM assembly parsing for two-operand form of 'mul' instruction.Jim Grosbach
Ongoing rdar://10435114. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144688 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15Thumb2 two-operand 'mul' instruction wide encoding parsing.Jim Grosbach
rdar://10449724 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144684 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and ↵Owen Anderson
VMOVv4f32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144683 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15Thumb2 assembly parsing for mul.w in IT block fix.Jim Grosbach
When the 3rd operand is not a low-register, and the first two operands are the same low register, the parser was incorrectly trying to use the 16-bit instruction encoding. rdar://10449281 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144679 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15ARM parsing datatype suffix variants for register-writeback VLD1/VST1 ↵Jim Grosbach
instructions. rdar://10435076 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144650 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15Fix typo in comment.Jay Foad
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144633 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15Make use of MachinePointerInfo::getFixedStack. This removes all mentionJay Foad
of PseudoSourceValue from lib/Target/. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144632 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15Remove some unnecessary includes of PseudoSourceValue.h.Jay Foad
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144631 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15Add vmov.f32 to materialize f32 immediate splats which cannot be handled byEvan Cheng
integer variants. rdar://10437054 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144608 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions.Jim Grosbach
rdar://10435076 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144606 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14ARM parsing datatype suffix variants for non-writeback VST1 instructions.Jim Grosbach
rdar://10435076 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144593 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14ARM parsing datatype suffix variants for non-writeback VLD1 instructions.Jim Grosbach
rdar://10435076 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144592 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14Add explanatory comment.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144589 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14Split out the plain '.{8|16|32|64}' suffix handling.Jim Grosbach
Make it easier to deal with aliases for instructions that do require a suffix but accept more specific variants of the same size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144588 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.Jim Grosbach
rdar://10435076 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144587 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14Supporting inline memmove isn't going to be worthwhile. The only way to avoidChad Rosier
violating a dependency is to emit all loads prior to stores. This would likely cause a great deal of spillage offsetting any potential gains. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144585 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14ARM VLDR/VSTR instructions don't need a size suffix.Jim Grosbach
Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14Add support for inlining small memcpys.Chad Rosier
rdar://10412592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144578 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14Fix a performance regression from r144565. Positive offsets were being loweredChad Rosier
into registers, rather then encoded directly in the load/store. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144576 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14ARM assembly parsing type suffix options for VLDR/VSTR.Jim Grosbach
rdar://10435076 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144575 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14Add support for Thumb load/stores with negative offsets.Chad Rosier
rdar://10412592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144565 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14Tidy up. 80 column.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144538 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14Add support for ARM halfword load/stores and signed byte loads with negativeChad Rosier
offsets. rdar://10412592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13The order in which the predicate is added differs between Thumb and ARM ↵Chad Rosier
mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144494 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing ↵Chad Rosier
failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144492 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13Fix comments.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144490 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13Add support for emitting both signed- and zero-extend loads. Fix Chad Rosier
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8 offsets (addressing mode 3). This enables a load followed by an integer extend to be folded into a single load. For example: ldrb r1, [r0] ldrb r1, [r0] uxtb r2, r1 => mov r3, r2 mov r3, r1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12build: Attempt to rectify inconsistencies between CMake and LLVMBuild ↵Daniel Dunbar
versions of explicit dependencies. - The hope is that we have a tool/test to verify these are accurate (and tight) soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144444 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12ARM refactor simple immediate asm operand render methods.Jim Grosbach
These immediate operands all use the same simple logic for rendering to MCInst, so have them share the method for doing so. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144439 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12Re-apply 144430, this time with the associated isel and disassmbler bits.Jim Grosbach
Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144437 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11Oops. Missed the isel half of this. revert while I sort that out.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144431 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11ARM assembly parsing for VST1 two-register encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144430 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11ARM optional size suffix for VLDR/VSTR syntax.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144427 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144426 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11ARM vldm and vstm VFP instructions can take a data type suffix.Jim Grosbach
It's ignored by the assembler when present, but is legal syntax. Other instructions have something similar, but for some mnemonics it's only sometimes not significant, so this quick check in the parser will need refactored into something more robust soon-ish. This gets some basics working in the meantime. Partial for rdar://10435264 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144422 91177308-0d34-0410-b5e6-96231b3b80d8
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