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2011-06-02Fix encoding for VEXTdf.Tanya Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Use TRI::has{Sub,Super}ClassEq() where possible.Jakob Stoklund Olesen
No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132455 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Don't hardcode the %reg format in the streamer.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132451 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31Fix ssat and ssat16 encodings for ARM and Thumb. The bit position valueBruno Cardoso Lopes
must be encoded decremented by one. Only add encoding tests for ssat16 because ssat can't be parsed yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132324 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-30Use the dwarf->llvm mapping to print register names in the cfiRafael Espindola
directives. Fixes PR9826. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132317 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.John McCall
This is important for the correct lowering of unwind instructions (which doesn't matter at all) and llvm.eh.resume calls (which does). Take 2, now with more basic competence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132295 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29I didn't mean to commit these residues of a personal project.John McCall
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132293 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.John McCall
This is important for the correct lowering of unwind instructions (which doesn't matter at all) and llvm.eh.resume calls (which does). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132291 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28Fix ARM fast isel to correctly flag memory operands to stores. This fixesCameron Zwarich
-verify-machineinstrs failures on several tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132268 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairsBruno Cardoso Lopes
to load/store i64 values. Since there's no current support to explicitly declare such restrictions, implement it by using specific hardcoded register pairs during isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132248 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28This actually starts at offset 0, not 1.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132246 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28Implement the 'M' output modifier for arm inline asm. This is fairlyEric Christopher
register allocation dependent and will occasionally break. WIP in the register allocator to model paired/etc registers. rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132242 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27Fix the remaining atomic intrinsics to use the right register classes on Thumb2,Cameron Zwarich
and add some basic tests for them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132235 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27ARM asm parser wasn't able to parse a "mov" instruction while in ThumbBruno Cardoso Lopes
mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode, default to the Thumb 1 versions/encodings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132233 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27Make size computation less brittle.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132222 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27Don't use movw / movt for iOS static codegen for now to workaround some ↵Evan Cheng
tools issues. rdar://9514789 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132211 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27Fix a silly mistake (which trips over an assertion) in r132099. rdar://9515076Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132194 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27Make the branch encoding for tBcc more obvious that it's a 4-byte opcodeEric Christopher
followed by a conditional and imm8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27Fix comment.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132178 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26Reorganize these slightly according to operand type.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132128 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26Mark tBX as an indirect branch rather than a return.Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132107 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25Rewrite fast-isel integer cast handling to handle more cases, and to be ↵Eli Friedman
simpler and more consistent. The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts). rdar://9437928 . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132099 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25Convert tBX_CALL / tBXr9_CALL to actual pseudoinstructions.Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132086 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25Clean up comment a bit.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132083 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25Implement the 'm' modifier. Note that it only works for memory operands.Eric Christopher
Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132081 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25Prepare ARMFastISel::SelectSIToFP for getRegForValue returning registers for ↵Eli Friedman
i8 and i16 values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132073 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25Restore an accidentally removed comment.Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132044 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25Move some code to a more logical place.Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132043 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. ThisCameron Zwarich
fixes <rdar://problem/9495913> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132042 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25Change the order of tBX's operands so that the predicate operands come after theCameron Zwarich
target register, matching BX. I filed this bug because I was confused at first: PR10007 - ARM branch instructions have inconsistent predicate operand placement <http://llvm.org/bugs/show_bug.cgi?id=10007> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132041 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25Rename tBX_Rm to tBX.Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132040 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25Rename the existing tBX/tBXr9 instructions to tBX_CALL/tBXr9_CALL to betterCameron Zwarich
reflect their actual meaning and match the ARM instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132039 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25Fix PR9762Bruno Cardoso Lopes
Enable the parsing of the operand "cpsr_all" for the ARM msr instruction git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24Implement the arm 'L' asm modifier.Eric Christopher
Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132024 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24Implement the immediate part of the 'B' modifier.Eric Christopher
Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132023 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24Add more unimplemented asm modifiers and some documentation of what theyEric Christopher
do. Part of rdar://9119939. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132015 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24Add support for the arm 'y' asm modifier.Eric Christopher
Fixes part of rdar://9444657 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132011 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-23Fix <rdar://problem/9476260> by having tail calls always generate 32-bit ↵Cameron Zwarich
branches in Darwin Thumb2 code. Tail calls are already disabled on Thumb1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131894 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-22RTABI chapter 4.3.4 specifies __eabi_mem* calls. Specifically, __eabi_memset ↵Renato Golin
accepts parameters (ptr, size, value) in a different order than GNU's memset (ptr, value, size), therefore the special lowering in AAPCS mode. Implementation by Evzen Muller. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131868 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-22Fix Bug 9386 - ARM disassembler failed to disassemble conditional bxJohnny Chen
Modified the patch to .td file supplied by Jyun-Yan You. Add a test case and modified ARMDisassemblerCore.cpp a little bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131859 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20adds some attributes to attribute section when cpu is "xscale"Rafael Espindola
(this is what used in Android NDK, when architecture is ARMv5) patch by Koan-Sin Tan git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131751 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20fixes target address tBL and tBLX and sets relocation typeRafael Espindola
of tBL/tBLX to R_ARM_THM_CALL (ARM ELF 4.7.1.6) Patch by koan-sin tan. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131748 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20Revert accidental commit.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131739 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20Revert r131664 and fix it in instcombine instead. rdar://9467055Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131708 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19This fixes one divergence between LLVM and binutils for ARM in theJason W Kim
text section. Assume the following bit of annotated assembly: .section .data.rel.ro,"aw",%progbits .align 2 .LAlpha: .long startval(GOTOFF) .text .align 2 .type main,%function .align 4 main: ;;; assume "main" starts at offset 0x20 0x0 push {r11, lr} 0x4 movw r0, :lower16:(.LAlpha-(.LBeta+8)) ;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8) ;;; ==> (??? - ((16-4) + 8) = -20 0x8 movt r0, :upper16:(.LAlpha-(.LBeta+8)) ;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8) ;;; ==> (??? - ((16-8) + 8) = -16 0xc ... blah .LBeta: 0x10 add r0, pc, r0 0x14 ... blah .LGamma: 0x18 add r1, pc, r1 Above snippet results in the following relocs in the .o file for the first pair of movw/movt instructions 00000024 R_ARM_MOVW_PREL_NC .LAlpha 00000028 R_ARM_MOVT_PREL .LAlpha And the encoded instructions in the .o file for main: must be 00000020 <main>: 20: e92d4800 push {fp, lr} 24: e30f0fec movw r0, #65516 ; 0xffec i.e. -20 28: e34f0ff0 movt r0, #65520 ; 0xfff0 i.e. -16 However, llc (prior to this commit) generates the following sequence 00000020 <main>: 20: e92d4800 push {fp, lr} 24: e30f0fec movw r0, #65516 ; 0xffec - i.e. -20 28: e34f0fff movt r0, #65535 ; 0xffff - i.e. -1 What has to happen in the ArmAsmBackend is that if the relocation is PC relative, the 16 bits encoded as part of movw and movt must be both addends, not addresses. It makes sense to encode addresses by right shifting the value by 16, but the result is incorrect for PIC. i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case. This change agrees with what GNU as does, and makes the PIC code run. MC/ARM/elf-movt.s covers this case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131674 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-1980 columns.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131649 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19Fixed sdiv and udiv for <4 x i16>. The test from r125402 still applies for ↵Mon P Wang
this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131630 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19Reuse the TargetInstrDesc.Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131625 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19Correctly constrain a register class when computing frame offsets, as the Thumb2Cameron Zwarich
add instruction takes an rGPR. This fixes the last of PR8825. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131619 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18Handle perfect shuffle case that generates a vrev for vectors of floats.Tanya Lattner
Add test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131582 91177308-0d34-0410-b5e6-96231b3b80d8
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