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2010-11-17Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,Evan Cheng
and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17make isVirtualSection a virtual method on MCSection. Chris' suggestion.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119547 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17More miscellaneous Thumb2 encodings.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119546 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17Add missing opcodes now that this function's used in more than one place.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119539 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17More ARM encoding bits. LDRH now encodes properly.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119529 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17Revert r119109 for now. It's breaking 176.gcc.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119492 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17Simplify code that toggle optional operand to ARM::CPSR.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119484 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17tidy upChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119462 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17The machine instruction no longer encodes the submode as a separate operand. WeBill Wendling
should get the submode from the load/store multiple instruction's opcode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119461 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17Proper encoding for VLDM and VSTM instructions. The register lists for theseBill Wendling
instructions have to distinguish between lists of single- and double-precision registers in order for the ASM matcher to do a proper job. In all other respects, a list of single- or double-precision registers are the same as a list of GPR registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119460 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17Add binary emission stuff for VLDM/VSTM. This reuses theBill Wendling
"getRegisterListOpValue" logic. If the registers are double or single precision, the value returned is suitable for VLDM/VSTM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-16Use the correct variable names so that the encodings will be correct.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119403 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-16ARM conditional mov encoding fix.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119354 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-16L_bit doesn't work here.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119325 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-16- Remove dead patterns.Bill Wendling
- Add encodings to the *LDMIA_RET instrs. Probably not needed... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119323 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-16vldm and vstm are mnemonics for vldmia and vstmia resp.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119321 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-16Encode the multi-load/store instructions with their respective modes ('ia',Bill Wendling
'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119310 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-16Add Thumb2 encodings for mov and friends.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119295 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15Attempt to provide encodings for some miscellaneous Thumb2 encodings.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119187 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15Code clean up. The peephole pass should be the one updating the instructionEvan Cheng
iterator, not TII->OptimizeCompareInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119186 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15Provide Thumb2 encodings for sxtb and friends.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119185 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15Recommit this change and remove the failing part of the test - it didn'tEric Christopher
pass in the first place and was masked by earlier failures not warning and aborting the block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119184 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119180 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15Add Thumb2 encodings for comparison and shift operators.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119176 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15Add correct Thumb2 encodings for mvn and friends.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119170 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15Add FIXMEs.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119167 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15Nuke redundant encoding bit set.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119164 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15add fields to the .td files unconditionally, simplifying tblgen a bit.Chris Lattner
Switch the ARM backend to use 'let' instead of 'set' with this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119120 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15Make sure ARM multi load / store pass copies memoperands when forming ldrd / ↵Evan Cheng
strd. pr8113. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119109 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15silence a ton of warnings from clang.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119102 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15Attempt to unbreak cmake-based buildsAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119098 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15First step of huge frame-related refactoring: move emit{Prologue,Epilogue} ↵Anton Korobeynikov
out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119097 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14trim #includes.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119075 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14rename LowerToMCInst -> LowerARMMachineInstrToMCInst.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119071 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14even more simplifications. ARM MCInstLowering is now justChris Lattner
a single function instead of a class. It doesn't need the complexity that X86 does. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119070 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14more shrinkificationChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119068 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14more simplifications.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119067 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14simplify and tidy upChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119066 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14stub out a powerpc MCInstPrinter implementation.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119059 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14Second attempt at providing correct encodings for Thumb2 binary operators.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119029 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13Comment out the defms until they're activated.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119000 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13Add uses of the *_ldst_multi multiclasses. These aren't used yet.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118999 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13Convert the modes to lower case.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118998 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13Minor cleanups:Bill Wendling
- Get the opcode once. - Add a ParserMatchClass to reglist. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118997 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13Add *_ldst_mult multiclasses to the ARM back-end. These will be used in theBill Wendling
future to separate out the ia, ib, da, db variants of the load/store multiple instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118995 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13MC: Simplify Mach-O and ELF object writer implementations.Daniel Dunbar
- What was I thinking????? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118992 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13Conditional moves are slightly more expensive than moves.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118985 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13Add conditional move of large immediate.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118968 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13Swap multiclass operand order for consistency with other patterns.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118965 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13Continue ARM indexed load refactoring. Multiclass for LDR{B} pre/post indexedJim Grosbach
instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118963 91177308-0d34-0410-b5e6-96231b3b80d8
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