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2012-03-22Added soft fail checks for the disassembler when decoding some corner cases ↵Silviu Baranga
of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153252 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or ↵Silviu Baranga
LDRSHT instruction on ARM git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153251 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22Added soft fail cases for the disassembler when decoding MUL instructions on ↵Silviu Baranga
ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153250 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add testKevin Enderby
case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153218 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Change conditional instructions definitions, e.g. ANDCC, ARMPseudoExpand and ↵Evan Cheng
t2PseudoExpand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153135 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20remove unused variableMatt Beaumont-Gay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153116 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Require a base pointer for stack realignment when SP may vary dynamically.Bob Wilson
ARMBaseRegisterInfo::canRealignStack was checking for variable-sized objects but not for stack adjustments around calls. Use hasReservedCallFrame() to check for both. The hasBasePointer function was already correctly checking both conditions, so the effect of this was that a base pointer would be used without checking whether the base pointer register could be reserved. I don't have a small testcase for this. <rdar://problem/11075906> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153110 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Remove some redundant checks.Bob Wilson
ARMFrameLowering::hasReservedCallFrame is already checking for variable sized objects, so there's no point in checking it twice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153109 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Fix assembling ARM vst2 instructions with double-spaced registers.Kevin Enderby
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153099 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20ARM non-scattered MachO relocations for movw/movt.Jim Grosbach
Needed when building -mdynamic-no-pic code. rdar://10459256 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153097 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20The ARM instructions that have an unpredictable behavior when the pc ↵Silviu Baranga
register operand is given now fail with soft fail. Modified the regression tests to reflect this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Test Commit - add a newlineRichard Barton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153083 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19ARM branch relaxation for unconditional t1 branches.Jim Grosbach
rdar://11059157 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153055 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19ARM assembly, accept optional '#' on lane index number.Jim Grosbach
rdar://11057160 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153053 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19Perform mul combine when multiplying wiht negative constants.Anton Korobeynikov
Patch by Weiming Zhao! This fixes PR12212 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153049 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17Reorder includes to match coding standards. Fix an issue or two exposed by that.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152978 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16Check if we can handle the arguments of a call (and therefore the call) inBill Wendling
fast-isel before emitting code. If the program bails after code was emitted, then it could lead to the stack being adjusted more than once (two CALLSEQ_BEGINs emitted) but being adjuste back only once after the call. This leads to general badness and gnashing of teeth. <rdar://problem/11050630> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152959 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16ARM fix silly typo in optional operand alias.Jim Grosbach
rdar://11065671 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152954 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16ARM divided syntax fmrx/fmxr mnemonics.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152946 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16ARM ldm/stm register lists can be out of order.Jim Grosbach
It's not a good style idea, as the registers will be laid down in memory in numerical order, not the order they're in the list, but it's legal. vldm/vstm are stricter. rdar://11064740 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152943 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16ARM optional operand on MRC/MCR assembly instructions.Jim Grosbach
rdar://11058464 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152883 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16ARM vmrs system registers mvfr0 and mvfr1 handling.Jim Grosbach
rdar://11058464 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152881 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15Remove inadvertant commit.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152870 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15[fast-isel] Address Eli's comments for r152847. Specifically, add a test caseChad Rosier
and still allow immediate encoding, just not with cmn. rdar://11038907 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152869 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15[fast-isel] Don't try to encode LONG_MIN using cmn instructions.Chad Rosier
rdar://11038907 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152847 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15ARM case-insensitive checking for APSR_nzcv.Jim Grosbach
rdar://11056591 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152846 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15ARM aliases for pre-unified syntax fcmpz[sd] mnemonics.Jim Grosbach
rdar://11056647 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152834 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15Use vmov.f32 to materialize f32 consts on ARM. This relaxes constraints onLang Hames
register allocation by allowing all 32 D-registers to be used. Patch by Cameron Zwarich. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152824 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15Fix VCVT decoding (between floating-point and fixed-point, Floating-point). ↵Kristof Beyls
Patch by Richard Barton. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-12Switch to unified syntax for VFP instructions in inline assembly.Bob Wilson
<rdar://problem/11024696> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152548 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-11Convert more static tables of registers used by calling convention to ↵Craig Topper
uint16_t to reduce space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152538 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-11Use uint16_t to store registers and opcode in static tables in the target ↵Craig Topper
specific backends. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152537 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-08Use uint16_t to store instruction implicit uses and defs. Reduces static data.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152301 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-08ARM don't use MCRelaxAll, as it's not safe on ARM.Jim Grosbach
The ARM code generator makes aggressive assumptions about the encodings being selected for branches which MCRelaxAll invalidates. rdar://11006355 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152268 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07[fast-isel] ARMEmitCmp generates FMSTAT, which transfers the floating-point Chad Rosier
condition flags to CPSR. This allows us to simplify SelectCmp. Patch by Zonr Chang <zonr.xchg@gmail.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152243 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07ARM pre-v6 assembly parsing for umull/smull.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152188 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07ARM pre-v6 alias for 'nop' to 'mov r0, r0'Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152185 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07Tidy up. Remove dead code that slipped into previous commit.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152184 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06ARM more NEON VLD/VST composite physical register refactoring.Jim Grosbach
Register pair, all lanes subscripting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152157 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06ARM refactor more NEON VLD/VST instructions to use composite physregsJim Grosbach
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the pseudos as a result. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152150 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Tidy up. Kill some dead code.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Allow the same types in DPair as in QPR.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152129 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.Kevin Enderby
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152127 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Add <imp-def> operands when reloading into physregs.Jakob Stoklund Olesen
When an instruction only writes sub-registers, it is still necessary to add an <imp-def> operand for the super-register. When reloading into a virtual register, rewriting will add the operand, but when loading directly into a virtual register, the <imp-def> operand is still necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152095 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Split fpscr into two registers: FPSCR and FPSCR_NZCV.Lang Hames
The fpscr register contains both flags (set by FP operations/comparisons) and control bits. The control bits (FPSCR) should be reserved, since they're always available and needn't be defined before use. The flag bits (FPSCR_NZCV) should like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152076 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05ARM vpush/vpop assembler mnemonics accept an optional size suffix.Jim Grosbach
rdar://10988114 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152068 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05ARM Refactor VLD/VST spaced pair instructions.Jim Grosbach
Use the new composite physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152063 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05ARM Remove a bit of dead code.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152061 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach
With the new composite physical registers to represent arbitrary pairs of DPR registers, we don't need the pseudo-registers anymore. Get rid of a bunch of them that use DPR register pairs and just use the real instructions directly instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152045 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05Make MCRegisterInfo available to the the MCInstPrinter.Jim Grosbach
Used to allow context sensitive printing of super-register or sub-register references. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152043 91177308-0d34-0410-b5e6-96231b3b80d8
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