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AgeCommit message (Expand)Author
2011-03-22Avoid -Wunused-variable in -asserts buildsMatt Beaumont-Gay
2011-03-21We need to pass the TargetMachine object to the InstPrinter if we are printingBill Wendling
2011-03-21Re-apply r127953 with fixes: eliminate empty return block if it has no predec...Evan Cheng
2011-03-19Revert r127953, "SimplifyCFG has stopped duplicating returns into predecessorsDaniel Dunbar
2011-03-19SimplifyCFG has stopped duplicating returns into predecessors to canonicalize IREvan Cheng
2011-03-19Fixed an assert by the ARM disassembler for LDRD_PRE/POST.Johnny Chen
2011-03-18Add support to the ARM asm parser for the register-shifted-register forms of ...Owen Anderson
2011-03-18Match a few more obvious patterns to revsh. rdar://9147637.Evan Cheng
2011-03-18Clean whitespace.Owen Anderson
2011-03-18Reduce code duplication.Owen Anderson
2011-03-18Thumb2 PC-relative loads require a fixup rather than just an immediate.Owen Anderson
2011-03-18The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset.Johnny Chen
2011-03-17There are two pseudos in this case that are Thumb mode, not one.Owen Anderson
2011-03-17It used to be that t_addrmode_s4 was used for both:Johnny Chen
2011-03-17Add "swi" which is an obsolete mnemonic for "svc".Nick Lewycky
2011-03-15There were two issues fixed:Johnny Chen
2011-03-15The VTBL (and VTBX) instructions are rather permissive concerning the masks theyBill Wendling
2011-03-15Some minor cleanups based on feedback.Bill Wendling
2011-03-15Do not form thumb2 ldrd / strd if the offset is by multiple of 4. rdar://9133587Evan Cheng
2011-03-15Fixed an ARM disassembler bug where it does not handle STRi12 correctly becau...Johnny Chen
2011-03-15Clean up ARM tail calls a bit. They're pseudo-instructions for normal branches.Jim Grosbach
2011-03-14Generate a VTBL instruction instead of a series of loads and stores when weBill Wendling
2011-03-14Remove some dead patterns.Jim Grosbach
2011-03-14Indentation.Evan Cheng
2011-03-12Sometimes isPredicable lies to us and tells us we don't need the operands.Eric Christopher
2011-03-12Add FIXME.Jim Grosbach
2011-03-12Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the sameJim Grosbach
2011-03-11Add a FIXME.Jim Grosbach
2011-03-11Pseudo-ize the ARM 'B' instruction.Jim Grosbach
2011-03-11Remove dead code. These ARM instruction definitions no longer exist.Jim Grosbach
2011-03-11Pseudo-ize VMOVDcc and VMOVScc.Jim Grosbach
2011-03-1180 columnsJim Grosbach
2011-03-11Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side-Jim Grosbach
2011-03-11ARM VDUPfd and VDUPfq can just be patterns. The instruction is the sameJim Grosbach
2011-03-11ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32qJim Grosbach
2011-03-11ARM VREV64df and VREV64qf can just be patterns. The instruction is the sameJim Grosbach
2011-03-11This FIXME has been fixed.Jim Grosbach
2011-03-11Properly pseudo-ize ARM MVNCCi.Jim Grosbach
2011-03-11Fix MOVCCi32imm to be have ARM-mode Requires and a proper size (8 bytes, was 4).Jim Grosbach
2011-03-11Properly pseudo-ize ARM MOVCCi and MOVCCi16.Jim Grosbach
2011-03-10Properly pseudo-ize MOVCCr and MOVCCs.Jim Grosbach
2011-03-10DMB can just be a pat referencing MCR.Jim Grosbach
2011-03-10Reorganize a bit. No functional change, just moving patterns up.Jim Grosbach
2011-03-10Pseudo-instructions are codegenonly by definition.Jim Grosbach
2011-03-09LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT.Johnny Chen
2011-03-09* Correct encoding for VSRI.Bill Wendling
2011-03-09Correct the encoding for VRSRA and VSRA instructions.Bill Wendling
2011-03-08* Fix VRSHR and VSHR to have the correct encoding for the immediate.Bill Wendling
2011-03-08Fix a compiler crash where a Glue value had multiple uses. Radar 9049552.Bob Wilson
2011-03-08Fix comment typos.Bob Wilson
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