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2010-08-30Expand MOVi32imm in ARM mode after regalloc. This providesAnton Korobeynikov
scheduling opportunities (extra instruction can go in between MOVT / MOVW pair removing the stall). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112546 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30Use the existing T2I_bin_s_irs pattern instead of creating T2I_bin_sw_irs, whichBill Wendling
is meant to do exactly the same thing. Thanks to Jim Grosbach for pointing this out! :-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112538 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30Remember to clear the shadow kill flag at the same time as clearing the realJakob Stoklund Olesen
kill flag. This could cause duplicate kill flags when the same register was used twice in a continuous sequence of STRs. There is no small test case. <rdar://problem/8218046> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112534 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30Remove NEON vmovn intrinsic, replacing it with vector truncate operations.Bob Wilson
Auto-upgrade the old intrinsic and update tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112507 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30Make ARM add rN, sp, #imm instructions rematerializable. That's how the ↵Jim Grosbach
address of locals is calculated, so this should help relieve register pressure a bit. Recalculating the local address is almost always going to be better than spilling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112503 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30When expanding NEON VST pseudo instructions, if the original super-registerBob Wilson
operand is killed, add it to the expanded instruction as an implicit kill operand instead of marking the individual subregs with kill flags. This should work better in general and also handles the case for VST3 where one of the subregs was not referenced in the expanded instruction and so was not marked killed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112494 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30Create Thumb2sI_cpsr and T2sI_cpsr. These new classes indicate that CPSR is theBill Wendling
optional modified register (instead of reg0). Along with r112461 it will make sure that the optional define of CPSR is marked as "def" and will thus mark the instructions using these classes (t2ANDS*) as setting the 's' flag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112462 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29Fix whitespaces. No functionality changes.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29Remove NEON vaddl, vaddw, vsubl, and vsubw intrinsics. Instead, use llvmBob Wilson
IR add/sub operations with one or both operands sign- or zero-extended. Auto-upgrade the old intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112416 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29- Add a parameter to T2I_bin_irs for those patterns which set the S bit.Bill Wendling
- Create T2I_bin_sw_irs to be like T2I_bin_w_irs, but that it sets the S bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112399 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29Name ANDflag to ANDS, which is less stupid.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112395 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29File missing from last commit.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112394 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29Create an ARMISD::AND node. This node is exactly like the "ARM::AND" node, butBill Wendling
it sets the CPSR register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112393 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28Use pseudo instructions for VST1 and VST2.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112357 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28We don't need to custom-select VLDMQ and VSTMQ anymore.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112336 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27When merging Thumb2 loads/stores, do not give up when the offset is one ofBob Wilson
the special values that for ARM would be used with IB or DA modes. Fall through and consider materializing a new base address is it would be profitable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112329 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just likeBob Wilson
all the other LDM/STM instructions. This fixes asm printer crashes when compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run with -O0 to check this in the future. Prior to this change VLDM/VSTM used addressing mode #5, but not really. The offset field was used to hold a count of the number of registers being loaded or stored, and the AM5 opcode field was expanded to specify the IA or DB mode, instead of the standard ADD/SUB specifier. Much of the backend was not aware of these special cases. The crashes occured when rewriting a frameindex caused the AM5 offset field to be changed so that it did not have a valid submode. I don't know exactly what changed to expose this now. Maybe we've never done much with -O0 and NEON. Regardless, there's no longer any reason to keep a count of the VLDM/VSTM registers, so we can use addressing mode #4 and clean things up in a lot of places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112322 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27Unsigned value cannot be < 0.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112300 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26Simplify eliminateFrameIndex() interface back down now that PEI doesn't needJim Grosbach
to try to re-use scavenged frame index reference registers. rdar://8277890 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112241 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26tidy up a bit. no functional change.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112228 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26Turn off the scavenging based frame reg reuse briefly to measure whether it'sJim Grosbach
still having a significant effect. It shouldn't be now that the pre-RA virtual base reg stuff is in. Assuming that's valididated by the nightly testers, we can simplify a lot of the PEI frame index code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112220 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26Use pseudo instructions for VST3.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112208 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26Reapply r112176 without removing the other CMN patterns (that was ↵Bill Wendling
unintentional). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112206 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26Restrict the register to tGPR to make sure the str instruction will beJim Grosbach
encodable as a 16-bit wide instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112195 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26Revert r112176; it broke test/CodeGen/Thumb2/thumb2-cmn.ll.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112191 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26There seems to be a (potential) hardware bug with the CMN instruction andBill Wendling
comparison with 0. These two pieces of code should give identical results: rsbs r1, r1, 0 cmp r0, r1 mov r0, #0 it ls mov r0, #1 and: cmn r0, r1 mov r0, #0 it ls mov r0, #1 However, the CMN gives the *opposite* result when r1 is 0. This is because the carry flag is set in the CMP case but not in the CMN case. In short, the CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the value of r0 and the carry bit (because the "carry bit" parameter to AddWithCarry is defined as 1 in this case, the carry flag will always be set when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is never a "carry" when this AddWithCarry is performed (because the "carry bit" parameter to AddWithCarry is defined as 0). The AddWithCarry in the CMP case seems to be relying upon the identity: ~x + 1 = -x However when x is 0 and unsigned, this doesn't hold: x = 0 ~x = 0xFFFF FFFF ~x + 1 = 0x1 0000 0000 (-x = 0) != (0x1 0000 0000 = ~x + 1) Therefore, we should disable *all* versions of CMN, especially when comparing against zero, until we can limit when the CMN instruction is used (when we know that the RHS is not 0) or when we have a hardware fix for this. (See the ARM docs for the "AddWithCarry" pseudo-code.) This is related to <rdar://problem/7569620>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112176 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26Use pseudo instructions for VST1d64Q.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112170 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26Enable pre-RA virtual frame base register allocation. rdar://8277890Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112127 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26Revert svn 107892 (with changes to work with trunk). It caused a crash ifBob Wilson
a VLD result was not used (Radar 8355607). It should also fix pr7988, but I haven't verified that yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112118 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25Start converting NEON load/stores to use pseudo instructions, beginning hereBob Wilson
with the VST4 instructions. Until after register allocation, we want to represent sets of adjacent registers by a single super-register. These VST4 pseudo instructions have a single QQ or QQQQ source register operand. They get expanded to the real VST4 instructions with 4 separate D register operands. Once this conversion is complete, we'll be able to remove the NEONPreAllocPass and avoid some fragile and hacky code elsewhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112108 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25Don't override the var from the enclosing scope.Jim Grosbach
When doing copy/paste/modify, it's apparently rather important to remember the 'modify' bit... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112075 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25ARM/Thumb2: Fix a misselect in getARMCmp, when attempting to adjust a signedDaniel Dunbar
comparison that would overflow. - The other under/overflow cases can't actually happen because the immediates which would trigger them are legal (so we don't enter this code), but adjusted the style to make it clear the transform is always valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112053 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25Do type checks before we bother to do everything else.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112039 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25Reorganize load mechanisms. Handle types in a little less fixed way.Eric Christopher
Fix some todos. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112031 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24Fix predicate and add a comment.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111981 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24Rework braindead conditionals I put in yesterday.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111974 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24Fix thumb2 mode loads to have the correct operand ordering. Add a todoEric Christopher
to fix this in the port. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111973 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24Add ARM heuristic for when to allocate a virtual base register for stackJim Grosbach
access. rdar://8277890&7352504 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111968 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24Move enabling the local stack allocation pass into the target where it belongs.Jim Grosbach
For now it's still a command line option, but the interface to the generic code doesn't need to know that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111942 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24add ARM cmd line option to force always using virtual base regs when possible.Jim Grosbach
Intended to help ease reproducing problems by increasing base register usage after heuristics for only using the when needed are in place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111930 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24Add comments for what the condition code symbols mean.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111889 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24Update comment.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111887 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24Fix the opcode and the operands for the load instruction.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111885 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24Add register class hack that needs to go away, but makes it more obviousEric Christopher
that it needs to go away. Use loadRegFromStackSlot where possible. Also, remember to update the value map. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111883 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24Add some more debugging code, make it more obvious that RegOffset isEric Christopher
getting an address for an object and select some default values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111871 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-23Don't need the extra register here.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111864 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-23Add some more "get address into register" code and a more TODOs/FIXMEs.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111860 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-23Add an ARMFunctionInfo member and use it.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-23Start getting ARM loads/address computation going.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111850 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-20Replace the arm.neon.vmovls and vmovlu intrinsics with vector sign-extend andBob Wilson
zero-extend operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111614 91177308-0d34-0410-b5e6-96231b3b80d8
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