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2011-12-22Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138>Bob Wilson
My change r146949 added register clobbers to the eh_sjlj_dispatchsetup pseudo instruction, but on Thumb1 some of those registers cannot be used. This caused massive failures on the testsuite when compiling for Thumb1. While fixing that, I noticed that the eh_sjlj_setjmp instruction has a "nofp" variant, and I realized that dispatchsetup needs the same thing, so I have added that as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147204 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).Jim Grosbach
rdar://10558523 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22Add missing usesCustomInserter flag on Int_eh_sjlj_setjmp_nofp.Bob Wilson
Noticed by inspection; I don't have a testcase for this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147188 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22Tidy up. Use predicate function a bit more liberally.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147184 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22Fix incorrect relocation generation. Patch by Kristof Beyls.Rafael Espindola
Fixes PR11214. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147180 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22ARM VFP add encoding of the bitcount to fixed-point<-->floating point. insns.Jim Grosbach
The value from the operands isn't right yet, but we weren't encoding it at all previously. The parser needs to twiddle the values when building the instruction. Partial for: rdar://10558523 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147170 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22Remove some bogus comments.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147169 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22ARM pre-UAL aliases. fcmp[sd].Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147158 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22ARM assembler should accept shift-by-zero for any shifted-immediate operand.Jim Grosbach
Just treat it as-if the shift wasn't there at all. 'as' compatibility. rdar://10604767 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147153 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22ARM assembly parser canonicallize on 'lsl' for shift-by-zero form.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147152 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22Tidy up. Trailing whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147151 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22Nuke invalid comment from copy/paste.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147150 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22Make the virtual methods in ARMELFObjectWriter public.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147132 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22Hopefully fix the cmake build.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147121 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22Fix name in comments.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147119 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22Unbreak cmake build after r147115.Richard Smith
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147117 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22Move the ARM specific parts of the ELF writer to Target/ARM.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147115 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21ARM NEON mnemonic aliase for vrecpeq.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147109 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21ARM VFP optional data type on VMOV GPR<-->SPR.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147104 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21ARM NEON optional data type on VSWP instructions.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147103 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21ARM NEON mnemonic aliases for vzipq and vswpq.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21ARM asm parser should be more lenient w/ .thumb_func directive.Jim Grosbach
Rather than require the symbol to be explicitly an argument of the directive, allow it to look ahead and grab the symbol from the next non-whitespace line. rdar://10611140 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147100 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21Thumb2 assembly parsing of 'mov rd, rn, rrx'.Jim Grosbach
Maps to the RRX instruction. Missed this case earlier. rdar://10615373 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147096 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21Thumb2 assembly parsing of 'mov(register shifted register)' aliases.Jim Grosbach
These map to the ASR, LSR, LSL, ROR instruction definitions. rdar://10615373 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147094 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21Move common code into an MRI function.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147071 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21ARM NEON assmebly parsing for VLD2 to all lanes instructions.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147069 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21Fix a couple of copy-n-paste bugs. Noticed by George Russell!Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147064 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21Reduce the exposure of Triple::OSType in the ELF object writer. This willRafael Espindola
avoid including ADT/Triple.h in many places when the target specific bits are moved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21Fix a couple of copy-n-paste bugs. Noticed by George Russell.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147032 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21ARM assembly parsing allows constant expressions for lane indices.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20ARM .req register name aliases are case insensitive, just like regnames.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147009 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Move comment to appropriate place.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147000 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Heed spill slot alignment on ARM.Jakob Stoklund Olesen
Use the spill slot alignment as well as the local variable alignment to determine when the stack needs to be realigned. This works now that the ARM target can always realign the stack by using a base pointer. Still respect the ARMBaseRegisterInfo::canRealignStack() function vetoing a realigned stack. Don't use aligned spill code in that case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20ARM assembly parsing and encoding for VST2 single-element, double spaced.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20ARM assembly parsing and encoding for VLD2 single-element, double spaced.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146983 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20ARM target code clean up. Check for iOS, not Darwin where it makes sense.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146981 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20First steps in ARM AsmParser support for .eabi_attribute and .archJason W Kim
(Both used for Linux gnueabi) No behavioral change yet (no tests need so far) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146977 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Fix up the CMake build for the new files added in r146960, they'reChandler Carruth
likely to stay either way that discussion ends up resolving itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146966 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Unweaken vtables as per ↵David Blaikie
http://llvm.org/docs/CodingStandards.html#ll_virtual_anch git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146960 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930.Bob Wilson
We used to rely on the *eh_sjlj_setjmp instructions to mark that a function with setjmp/longjmp exception handling clobbers all the registers. But with the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are expanded away earlier, before PEI can see them to determine what registers to save and restore. Mark the dispatchsetup instruction in the same way, since that instruction cannot be expanded early. This also more accurately reflects when the registers are clobbered. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146949 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20ARM assembly shifts by zero should be plain 'mov' instructions.Jim Grosbach
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's not strictly legal UAL syntax. It's a common extension and the friendly thing to do. rdar://10604663 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146937 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates.Jim Grosbach
e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117" rdar://10603913 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146925 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19ARM assembly parsing and encoding support for LDRD(label).Jim Grosbach
rdar://9932658 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19ARM NEON two-operand aliases for VPADD.Jim Grosbach
rdar://10602276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19ARM VFP pre-UAL mnemonic aliases for fmul[sd].Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146892 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd].Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146887 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19ARM NEON implied destination aliases for VMAX/VMIN.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146885 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19ARM NEON relax parse time diagnostics for alignment specifiers.Jim Grosbach
There's more variation that we need to handle. Error checking will need to be on operand predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19Tidy up.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146882 91177308-0d34-0410-b5e6-96231b3b80d8
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