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2012-02-05DefinesPredicate should only look for def operands. Patch by Ludwig Meier.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149846 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05Persuade GCC that there is nothing worth warning about here (there isn't).Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149834 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-04TargetPassConfig: confine the MC configuration to TargetMachine.Andrew Trick
Passes prior to instructon selection are now split into separate configurable stages. Header dependencies are simplified. The bulk of this diff is simply removal of the silly DisableVerify flags. Sorry for the target header churn. Attempting to stabilize them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149754 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03[fast-isel] Add support for URem.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149716 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03[fast-isel] Rename isZExt to isSigned. No functional change intended.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149714 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03[fast-isel] Add support for UDIV.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149712 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03[fast-isel] Add support for FPToUI. Also add test cases for FPToSI.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149706 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03[fast-isel] Add support for selecting UIToFP.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149704 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03Added TargetPassConfig. The first little step toward configuring codegen passes.Andrew Trick
Allows command line overrides to be centralized in LLVMTargetMachine.cpp. LLVMTargetMachine can intercept common passes and give precedence to command line overrides. Allows adding "internal" target configuration options without touching TargetOptions. Encapsulates the PassManager. Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs. Allows modifying the target configuration hooks without rebuilding the world. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149672 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02Add pseudo-registers for pairs, triples, and quads of D registers.Jakob Stoklund Olesen
NEON loads and stores accept single and double spaced pairs, triples, and quads of D registers. This patch adds new register classes to accurately model those constraints: Dn, Dn+1 Dn, Dn+2 ---------------------- DPair DPairSpc DTriple DTripleSpc DQuad DQuadSpc Also extend the existing QQ and QQQQ register classes to contains all Q pairs and quads instead of just the aligned ones. These new register classes will make it possible to accurately model constraints on NEON loads and stores, and we can get rid of all the NEON pseudo-instructions. The late scheduler will be able to accurately model instruction dependencies from the explicit operands. This more than doubles the number of ARM registers, but the backend passes are quite good at handling this. The llc -O0 compile time only regresses by 1.5%. Future work on register mask operands will recover this regression. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149640 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01Move ARM subreg index compositions to the SubRegIndex itself.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149557 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31Tidy up. One more return type mismatch fix.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149452 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31Refactor loop for better readability.Jim Grosbach
Excellent suggestion from Ben Kramer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149417 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31Add explanatory comment.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149416 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-29Cleanups for EABI standard functionsAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149195 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-29Use base AAPCS for varargs functions even for AAPCS-VFP CCAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149194 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-28Add a note about a potential optimization for clz/ctz patterns for ARMBob Wilson
(and other targets). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149182 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-28Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM ↵James Molloy
and MIPS ELF backends. Fixes PR11877 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149180 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-27Better user diagnostics for more ARM MachO relocation errors.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149102 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26Keep source information, if available, around for ARM Fixups.Jim Grosbach
Adjust an example MachObjectWriter diagnostic to use the information to issue a better message. Before: LLVM ERROR: unknown ARM fixup kind! After: x.s:6:5: error: unsupported relocation on symbol beq bar ^ rdar://9800182 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149093 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26Tidy up. Fix mismatched return types for error handling.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149062 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26Add support for the R_ARM_TARGET1 relocation, which should be given to ↵James Molloy
relocations applied to all C++ constructors and destructors. This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149057 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25Properly emit ctors / dtors with priorities into desired sectionsAnton Korobeynikov
and let linker handle the rest. This finally fixes PR5329 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148990 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25ARM assemly parsing and validation of IT instruction.Jim Grosbach
"Although a Thumb2 instruction, the IT mnemonic shall be permitted in ARM mode, and the condition verified to match the condition code(s) on the following instruction(s)." PR11853 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148969 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25NEON VLD4(all lanes) assembly parsing and encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148884 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Tidy up. Rename VLD4DUP patterns for consistency.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148883 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24NEON VLD3(all lanes) assembly parsing and encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148882 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24NEON VST4(one lane) assembly parsing and encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148836 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Widen the instruction encoder that TblGen emits to a 64 bits, which should ↵Owen Anderson
accomodate every target I can think of offhand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148833 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24NEON VLD4(one lane) assembly parsing and encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148832 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24NEON Two-operand assembly aliases for VSRA.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148821 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24NEON Two-operand assembly aliases for VSLI.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148819 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24NEON Two-operand assembly aliases for VSRI.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148818 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24NEON add correct predicates for some asm aliases.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148815 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Use correct register class for am2offset register operands.Anton Korobeynikov
This pacifies machine verifier git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148782 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24NEON VST4(multiple 4 element structures) assembly parsing.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148764 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24NEON VLD4(multiple 4 element structures) assembly parsing.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148762 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Tidy up. Remove some vertical space for readability.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148761 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Revert r148686 (and r148694, a fix to it) due to a serious layeringChandler Carruth
violation -- MC cannot depend on CodeGen. Specifically, the MCTargetDesc component of each target is actually a subcomponent of the MC library. As such, it cannot depend on the target-independent code generator, because MC itself cannot depend on the target-independent code generator. This change moved a flag from the ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in ARMException.cpp, leaving behind an 'extern' to refer back to it. That layering order isn't viable givin the constraints outlined above. Commandline flags are designed to be static specifically to avoid these types of bugs. Fixing this is likely going to require some non-trivial refactoring. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148759 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Fix typo.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148757 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24NEON VST3(single element from one lane) assembly parsing.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148755 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23NEON VST3(multiple 3-element structures) assembly parsing.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148748 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23NEON VLD3(multiple 3-element structures) assembly parsing.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148745 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23Add missed mayStore flag to STREXD / t2STREXDAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148742 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23NEON VLD3 lane-indexed assembly parsing and encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148734 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23Simplify some NEON assembly pseudo definitions.Jim Grosbach
Let the generic token alias definitions handle the data subtype suffices. We don't need explicit versions for each. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148718 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23ARMAsmPrinter.cpp: Try to fix up r148686. EnableARMEHABI was also here.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148694 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23An option to selectively enable parts of ARM EHABI support.Evgeniy Stepanov
This change adds an new value to the --arm-enable-ehabi option that disables emitting unwinding descriptors. This mode gives a working backtrace() without the (currently broken) exception support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148686 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-22Add fused multiple+add instructions from VFPv4.Anton Korobeynikov
Patch by Ana Pazos! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148658 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-21Thumb2 'add rd, pc, imm' alternate form for 'adr' instruction.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148601 91177308-0d34-0410-b5e6-96231b3b80d8
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