aboutsummaryrefslogtreecommitdiff
path: root/lib/Target/ARM
AgeCommit message (Collapse)Author
2012-02-27ARM BL/BLX instruction fixups should use relocations.Jim Grosbach
We on the linker to resolve calls to the appropriate BL/BLX instruction to make interworking function correctly. It uses the symbol in the relocation to do that, so we need to be careful about being too clever. To enable this for ARM mode, split the BL/BLX fixup kind off from the unconditional-branch fixups. rdar://10927209 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151571 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27Fix the symbolic operand added for the C disassmbler API for the ARM blKevin Enderby
thumb instruction. The PC adjustment is +4 in Thumb mode and +8 in ARM mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151530 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24Remove unused cl::opt, make another opt static.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151398 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24Thumb2 asm aliases for wide bitwise w/ immediate instructions.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151384 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24comment fixJia Liu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151339 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24Switch ARM target to register masks.Jakob Stoklund Olesen
I'll let the buildbots determine the compile time improvements from this change, but 464.h264ref has 5% faster codegen at -O2. This patch does cause some assembly changes. Branch folding can make different decisions about calls with dead return values. CriticalAntiDepBreaker may choose different registers because its liveness tracking is affected. MachineCopyPropagation may sometimes leave a dead copy behind. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151331 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24Make sure the regs are low regs for tMUL size reduction.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151318 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24Thumb2 size reduction fix for tied operands of tMUL.Jim Grosbach
The tied source operand of tMUL is the second source operand, not the first like every other two-address thumb instruction. Special case it in the size reduction pass to make sure we create the tMUL instruction properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151315 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24When emitting a cmp with 0 for a lowered select, mask out the highDan Gohman
bits of the value carying the boolean condition, as their contents are undefined. This fixes rdar://10887484. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151310 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23Updated the llvm-mc disassembler C API to support for the X86 target.Kevin Enderby
rdar://10873652 As part of this I updated the llvm-mc disassembler C API to always call the SymbolLookUp call back even if there is no getOpInfo call back. If there is a getOpInfo call back that is tried first and then if that gets no information then the SymbolLookUp is called. I also made the code more robust by memset(3)'ing to zero the LLVMOpInfo1 struct before then setting SymbolicOp.Value before for the call to getOpInfo. And also don't use any values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't use any of the ReferenceType or ReferenceName values from SymbolLookUp if it returns NULL. rdar://10873563 and rdar://10873683 For the X86 target also fixed bugs so the annotations get printed. Also fixed a few places in the ARM target that was not producing symbolic operands for some instructions. rdar://10878166 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151267 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23Remove unused variable.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151251 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high 16 bitsEvan Cheng
of x are zero. This optimizes rev + lsr 16 to rev16. rdar://10750814 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151230 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23Optimize a couple of common patterns involving conditional moves where the falseEvan Cheng
value is zero. Instead of a cmov + op, issue an conditional op instead. e.g. cmp r9, r4 mov r4, #0 moveq r4, #1 orr lr, lr, r4 should be: cmp r9, r4 orreq lr, lr, #1 That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y). It's possible to extend this to ADD and SUB but I don't think they are common. rdar://8659097 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151224 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22Remove extra semi-colons.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151169 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22Make all pointers to TargetRegisterClass const since they are all pointers ↵Craig Topper
to static data that should not be modified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22Clarify ARM calling conventions.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151113 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-21Calls don't really change the stack pointer.Jakob Stoklund Olesen
Even if a call instruction has %SP<imp-def> operands, it doesn't change the value of the stack pointer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151104 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-21Proper support for a bastardized darwin-eabi hybird ABI.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151083 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-20Improve generated code for extending loads and some trunc stores on ARM.James Molloy
Teach TargetSelectionDAG about lengthening loads for vector types and set v4i8 as legal. Allow FP_TO_UINT for v4i16 from v4i32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150956 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-19Remove dead code. Improve llvm_unreachable text. Simplify some control flow.Ahmed Charles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150918 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-19comment fix ARM.hJia Liu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150904 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-18Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu
MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17Handle regmask operands in ARMInstrInfo.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150833 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17Fix ARMBaseInstrInfo::getInstrLatency for calls.Jakob Stoklund Olesen
Calls always clobber CPSR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150831 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17[fast-isel] Add support for returning non-legal types with no sign- or zero-Chad Rosier
entend flag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150774 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17Re-enable 150652 and 150654 - Make FPSCR non-reserved, and make MachineCSE ↵Lang Hames
bail on reserved registers. This *should* be safe as of r150786. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150769 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16Remove unnecessary assignment to temporary, ResultReg.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150737 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16Oop - r150653 + r150654 broke one of my test cases. Backing out for now...Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150655 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16FPSCR shouldn't be reserved.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150654 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Add braces to if clause to make symmetric with associate else clause.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150591 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Strip the pointer casts from the constants here.Bill Wendling
The c'tor list is stored as a list of 'void ()*'s, so all of the functions are bitcast to that. However, the dyn_cast doesn't automagically look through bitcasts. Do that for it. <rdar://problem/10813350> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150572 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Use a temporary variable, rather then a series of redundant calls.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150536 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Remove unnecessary assignment to temporary, ResultReg.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150520 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Third time's the charm...?Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150447 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Unswap swap operands, partially reducing confusion.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150444 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Don't reserve the R0 and R1 registers here. We don't use these registers, andBill Wendling
marking them as "live-in" into a BB ruins some invariants that the back-end tries to maintain. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150437 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Make operands for VSWP read-modify-write.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150433 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11Make the EDis tables const.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150304 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Revert r150222, as the clang driver now handles this properly.Jim Grosbach
Now that the clang driver passes the CPU and feature information to the backend when processing assembly files (150273), this isn't necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150274 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Make valgrind happy.Jason W Kim
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150251 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10ARM on darwin, v6 implies the presence of VFP for the assembler.Jim Grosbach
rdar://10838899 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150222 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09Teach the MC and disassembler about SoftFail, and hook it up to ↵James Molloy
UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150169 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08Codegen pass definition cleanup. No functionality.Andrew Trick
Moving toward a uniform style of pass definition to allow easier target configuration. Globally declare Pass ID. Globally declare pass initializer. Use INITIALIZE_PASS consistently. Add a call to the initializer from CodeGen.cpp. Remove redundant "createPass" functions and "getPassName" methods. While cleaning up declarations, cleaned up comments (sorry for large diff). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150100 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08[fast-isel] Add support for SUBs with non-legal types.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150047 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08[fast-isel] Add support for ORs with non-legal types.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150045 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-07[fast-isel] Add support for indirect branches.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150014 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-07Do not fold ADD / SUB into load / store (to form pre-indexed, post-indexedEvan Cheng
load / store) if the ADD / SUB has a live definition of CPSR. Bug reported by David Meyer. Alas, no test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149970 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-07Convert assert(0) to llvm_unreachableCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-06[fast-isel] Add support for ADDs with non-legal types.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149934 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-06Enable streaming of bitcodeDerek Schuff
This CL delays reading of function bodies from initial parse until materialization, allowing overlap of compilation with bitcode download. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149918 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-09-25 11:27:08 +0000