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2011-03-24--- Merging r128203 into '.':Bill Wendling
U lib/Target/ARM/ARMBaseInstrInfo.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@128207 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24--- Merging r127981 into '.':Bill Wendling
U include/llvm/Target/TargetLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86ISelLowering.h U lib/Target/ARM/ARMISelLowering.h U lib/Target/ARM/ARMISelLowering.cpp U lib/Transforms/Scalar/CodeGenPrepare.cpp --- Merging r128194 into '.': G lib/Transforms/Scalar/CodeGenPrepare.cpp --- Merging r128196 into '.': G lib/Transforms/Scalar/CodeGenPrepare.cpp --- Merging r128197 into '.': A test/CodeGen/X86/tailcall-returndup-void.ll G lib/Transforms/Scalar/CodeGenPrepare.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@128200 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22--- Merging r128100 into '.':Bill Wendling
U lib/Target/ARM/ARMFastISel.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@128101 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-08Fix a compiler crash where a Glue value had multiple uses. Radar 9049552.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127198 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-08Fix comment typos.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127197 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-07Rename the narrow shift right immediate operands to "shr_imm*" operands. AlsoBill Wendling
expand the testing of the narrowing shift right instructions. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127193 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-07Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127175 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05ARM assembler stuff is crazy: for .setfp positive values of offset ↵Anton Korobeynikov
corresponds to "add" instruction, not to "sub" as in .pad case git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05In Thumb1 mode the constant might be materialized via the load from ↵Anton Korobeynikov
constpool. Emit unwinding information in case when this load from constpool is used to change the stack pointer in the prologue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05Implement frame unwinding information emission for Thumb1. Not finished yet ↵Anton Korobeynikov
because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127104 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05Add unwind information emission for thumb stuffAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127103 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05Handle MI flags inside Thumb2SizeReduction pass.Anton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05Preliminary support for ARM frame save directives emission via MI flags.Anton Korobeynikov
This is just very first approximation how the stuff should be done (e.g. ARM-only for now). More to follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127101 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05Some first rudimentary support for ARM EHABI: print exception table in "text ↵Anton Korobeynikov
mode". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127099 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05Remove unused conditional negate operations.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127090 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04Disable ARMGlobalMerge on darwin. The debugger is not yet able to extract ↵Devang Patel
individual variable's info from merged global. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127019 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03PR8053: Fix encoding of S bit in some ARM instructions.Bob Wilson
Patch by Zonr Chang! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126967 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03Add a readme entry for the redundant movw issue for pr9370.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126930 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03pr9367: Add missing predicated BLX instructions.Bob Wilson
Patch by Jyun-Yan You, with some minor adjustments and a testcase from me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126915 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-02Fixes an assertion failure while disassembling ARM rsbs reg/reg form.Kevin Enderby
Patch by Ted Kremenek! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-02Fixing a bug when printing fpu text to object file. Patch by Mans Rullgard.Renato Golin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126882 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-01Narrow right shifts need to encode their immediates differently from a normalBill Wendling
shift. 16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0> 32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0> 64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28Fix .fpu printing in ARM assembly, regarding bug ↵Renato Golin
http://llvm.org/bugs/show_bug.cgi?id=8931 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28Add missing whitespace in the formatting.Kevin Enderby
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126687 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28Fix the arm's disassembler for blx that was building an MCInst without theKevin Enderby
needed two predicate operands before the imm operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126662 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28Fix a typo which cause dag combine crash. rdar://9059537.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126661 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28Support for byval parameters on ARM. Will be enabled by a forthcomingStuart Hastings
patch to the front-end. Radar 7662569. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126655 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-25Add patterns to use post-increment addressing for Neon VST1-lane instructions.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126477 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-25Fix typo.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126467 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-25Each prologue may have multiple vpush instructions to store callee-savedEvan Cheng
D registers since the vpush list may not have gaps. Make sure the stack adjustment instruction isn't moved between them. Ditto for vpop in epilogues. Sorry, can't reduce a small test case. rdar://9043312 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126457 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-23Change VFPNeonA8 definition to make the code easier to read.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126298 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-23More fcopysign correctness and performance fix.Evan Cheng
The previous codegen for the slow path (when values are in VFP / NEON registers) was incorrect if the source is NaN. The new codegen uses NEON vbsl instruction to copy the sign bit. e.g. vmov.i32 d1, #0x80000000 vbsl d1, d2, d0 If NEON is not available, it uses integer instructions to copy the sign bit. rdar://9034702 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126295 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-22VFP single precision arith instructions can go down to NEON pipeline, but on ↵Evan Cheng
Cortex-A8 only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126238 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-22Guard against de-referencing MBB.end().Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126192 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-22available_externally (hidden or not) GVs are always accessed via stubs. ↵Evan Cheng
rdar://9027648. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126191 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-22Only use blx for external function calls on thumb, these could be fixedEric Christopher
up by the dynamic linker, but it's better to use the correct instruction to begin with. Fixes rdar://9011034 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126176 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-21Skipping over debugvalue instructions to determine whether the split spot is ↵Evan Cheng
in a IT block. rdar://9030770 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126159 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-21Revert r124611 - "Keep track of incoming argument's location while emitting ↵Devang Patel
LiveIns." In other words, do not keep track of argument's location. The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body. This requires some coordination with debugger to get this working. - The debugger needs to be aware of prolog_end attribute attached with line table entries. - The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126155 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-20Use explicit add_subdirectory's for LLVM target sublibraries insteadOscar Fuentes
of testing for its presence at cmake time. This way the build automatically regenerates the makefiles when a svn update brings in a new sublibrary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126068 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-19Avoid dangling else warnings.Joerg Sonnenberger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-18Fix style and a typoBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125949 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-18Add assembly parsing support for "msr" and also fix its encoding. Also addBruno Cardoso Lopes
testcases for the disassembler to make sure it still works for "msr". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125948 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-17Triple::MinGW64 is deprecated and removed. We can use Triple::MinGW32 generally.NAKAMURA Takumi
No one uses *-mingw64. mingw-w64 is represented as {i686|x86_64}-w64-mingw32. In llvm side, i686 and x64 can be treated as similar way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125747 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-16Some single precision VFP instructions may be executed on NEON pipeline, but ↵Evan Cheng
not double precision ones. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125624 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-15Teach ARMLoadStoreOptimizer to remove kill flags from merged instructions as ↵Jakob Stoklund Olesen
well. This is necessary to avoid a crash in certain tangled situations where a kill flag is first correctly moved to a merged instruction, and then needs to be moved again: STR %R0, a... STR %R0<kill>, b... First becomes: STR %R0, b... STM a, %R0<kill>, ... and then: STM a, %R0, ... STM b, %R0<kill>, ... We can now remove the kill flag from the merged STM when needed. 8960050. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-15Spelling fix: consequtive -> consecutive.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125563 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-14Remove unused bitvectors that record ARM callee-saved registers.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125534 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-14A fail to match coprocessor number and register number must fail instead of ↵Bruno Cardoso Lopes
assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125521 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-14Fix encoding and add parsing support for the arm/thumb CPS instruction:Bruno Cardoso Lopes
- Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125489 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-13Enhance ComputeMaskedBits to know that aligned frameindexesChris Lattner
have their low bits set to zero. This allows us to optimize out explicit stack alignment code like in stack-align.ll:test4 when it is redundant. Doing this causes the code generator to start turning FI+cst into FI|cst all over the place, which is general goodness (that is the canonical form) except that various pieces of the code generator don't handle OR aggressively. Fix this by introducing a new SelectionDAG::isBaseWithConstantOffset predicate, and using it in places that are looking for ADD(X,CST). The ARM backend in particular was missing a lot of addressing mode folding opportunities around OR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125470 91177308-0d34-0410-b5e6-96231b3b80d8
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