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path: root/lib/Target/ARM/Thumb1RegisterInfo.cpp
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2010-08-10Re-apply r110655 with fixes. Epilogue must restore sp from fp if the ↵Evan Cheng
function stack frame has a var-sized object. Also added a test case to check for the added benefit of this patch: it's optimizing away the unnecessary restore of sp from fp for some non-leaf functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110707 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FPDaniel Dunbar
register is", it breaks a couple test-suite tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110701 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Fix ARM hasFP() semantics. It should return true whenever FP register isEvan Cheng
reserved, not available for general allocation. This eliminates all the extra checks for Darwin. This change also fixes the use of FP to access frame indices in leaf functions and cleaned up some confusing code in epilogue emission. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110655 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20Constify some arguments.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108812 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11Make getPhysicalRegisterRegClass non-virtual. Should be able to remove it soon.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29skip dbg_value instructionsJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107154 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04rdar://7937137 - dbg values not being handled in thumb1 version ofJim Grosbach
eliminateFrameIndex(), leading to llvm_unreachable() assertion failure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102980 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15ReuseFrameIndexVals is used in multiple files, so it can't be static.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101379 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15Add const qualifiers to CodeGen's use of LLVM IR constructs.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-13Change ARM ld/st multiple instructions to have variant instructions forBob Wilson
writebacks to the address register. This gets rid of the hack that the first register on the list was the magic writeback register operand. There was an implicit constraint that if that operand was not reg0 it had to match the base register operand. The post-RA scheduler's antidependency breaker did not understand that constraint and sometimes changed one without the other. This also fixes Radar 7495976 and should help the verifier work better for ARM code. There are now new ld/st instructions explicit writeback operands and explicit constraints that tie those registers together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98409 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-10comment why we use custom epilogue for t1 functions using vaargs.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98182 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-10Clear up the last (famous last words) frame index value reuse issues for Thumb1.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98109 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-09Change the Value argument to eliminateFrameIndex to a type-tagged value. ThisJim Grosbach
is preparatory to having PEI's scavenged frame index value reuse logic properly distinguish types of frame values (e.g., whether the value is stack-pointer relative or frame-pointer relative). No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98086 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-09scavenged frame index value re-use gets confused when more than one baseJim Grosbach
register is involved for thumb1. Work around this for the moment by only re-using SP-relative offsets. This is temporary 'til the code can distinguish multiple base registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98071 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-06Thumb1 epilogue code generation needs to take into account that callee-savedJim Grosbach
registers may be restored via a pop instruction, not just a tRestore. This fixes nightly test 471.omnetep for Thumb1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97867 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-24handle very large call frames when require SPAdj != 0 for Thumb1Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97013 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-19Remove predicates when changing an add into an unpredicable mov.Jakob Stoklund Olesen
Since the mov is executed unconditionally, make sure that the add didn't have any predicate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93909 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-03improve portability to avoid conflicting with std::next in c++'0x.Chris Lattner
Patch by Howard Hinnant! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90365 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-09Use Unified Assembly Syntax for the ARM backend.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-0780-column cleanup of file header commentsJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86408 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-28Cleanup now that frame index scavenging via post-pass is working for ARM and ↵Jim Grosbach
Thumb2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85406 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22Trim more includes.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84832 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21Missing piece of the ARM frame index post-scavenging conditionalizationJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84798 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20Now that all ARM subtargets use frame index scavenging, the Thumb1 requires*Jim Grosbach
functions are not needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84587 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19Enable allocation of R3 in Thumb1Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84563 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19Adjust the scavenge register spilling to allow the target to choose anJim Grosbach
appropriate restore location for the spill as well as perform the actual save and restore. The Thumb1 target uses this to make sure R12 is not clobbered while a spilled scavenger register is live there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84554 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08Cleanup up unused R3LiveIn tracking.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83522 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08Re-enable register scavenging in Thumb1 by default.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83521 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07reverting thumb1 scavenging default due to test failure while I figure out ↵Jim Grosbach
what's up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83501 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07Enable thumb1 register scavenging by default.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83494 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07Add register-reuse to frame-index register scavenging. When a target usesJim Grosbach
a virtual register to eliminate a frame index, it can return that register and the constant stored there to PEI to track. When scavenging to allocate for those registers, PEI then tracks the last-used register and value, and if it is still available and matches the value for the next index, reuses the existing value rather and removes the re-materialization instructions. Fancier tracking and adjustment of scavenger allocations to keep more values live for longer is possible, but not yet implemented and would likely be better done via a different, less special-purpose, approach to the problem. eliminateFrameIndex() is modified so the target implementations can return the registers they wish to be tracked for reuse. ARM Thumb1 implements and utilizes the new mechanism. All other targets are simply modified to adjust for the changed eliminateFrameIndex() prototype. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83467 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-05In Thumb1, the register scavenger is not always able to use an emergencyJim Grosbach
spill slot. When frame references are via the frame pointer, they will be negative, but Thumb1 load/store instructions only allow positive immediate offsets. Instead, Thumb1 will spill to R12. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83336 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01ARM::tPOP and tPOP_RET each has an extra writeback operand now.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83214 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-24Start of revamping the register scavenging in PEI. ARM Thumb1 is the drivingJim Grosbach
interest for this, as it currently reserves a register rather than using the scavenger for matierializing constants as needed. Instead of scavenging registers on the fly while eliminating frame indices, new virtual registers are created, and then a scavenged collectively in a post-pass over the function. This isolates the bits that need to interact with the scavenger, and sets the stage for more intelligent use, and reuse, of scavenged registers. For the time being, this is disabled by default. Once the bugs are worked out, the current scavenging calls in replaceFrameIndices() will be removed and the post-pass scavenging will be the default. Until then, -enable-frame-index-scavenging enables the new code. Currently, only the Thumb1 back end is set up to use it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82734 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-06Remove some unused variables and methods warned about byDuncan Sands
icc (#177, partial). Patch by Erick Tryzelaar. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81106 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-13Push LLVMContexts through the IntegerType APIs.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78948 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11Shrinkify Thumb2 load / store multiple instructions.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78717 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11Whitespace cleanup. Remove trailing whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78666 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson
own struct type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-28tADDrSPI doesn't have a predicate operand, but tADDhirr and tADDi3 have.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77305 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-28- More refactoring. This gets rid of all of the getOpcode calls.Evan Cheng
- This change also makes it possible to switch between ARM / Thumb on a per-function basis. - Fixed thumb2 routine which expand reg + arbitrary immediate. It was using using ARM so_imm logic. - Use movw and movt to do reg + imm when profitable. - Other code clean ups and minor optimizations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77300 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-26Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a ↵Evan Cheng
low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77172 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-26Refactor. Get rid of a few more getOpcode() calls.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77164 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-24Revert the ConstantInt constructors back to their 2.5 forms where possible, ↵Owen Anderson
thanks to contexts-on-types. More to come. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77011 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-24Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index ↵David Goodwin
elimination more exactly for Thumb-2 to get better code gen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76919 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-22Get rid of the Pass+Context magic.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76702 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-20Fix PR4567. Thumb1 target was using the wrong instruction to handle sp = sub ↵Evan Cheng
fp, #c. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76401 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-19Fix a regression from 76124. Thumb1 instructions default to S bit being true.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76374 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16Emit cross regclass register moves for thumb2.Anton Korobeynikov
Minor code duplication cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76124 91177308-0d34-0410-b5e6-96231b3b80d8
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