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path: root/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
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2013-01-14Follow up of commit r172472.Quentin Colombet
Refactor the big if/else sequence into one string switch for ARM subtype selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172475 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-14Complete the existing support of ARM v6m, v7m, and v7em, i.e., respectively ↵Quentin Colombet
cortex-m0, cortex-m3, and cortex-m4 on the backend side. Adds new subtype values for the MachO format and use them when the related triple are set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172472 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-08Renamed MCInstFragment to MCRelaxableFragment and added some comments.Eli Bendersky
No change in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171822 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05Correct ARM NOP encodingDavid Sehr
The encoding of NOP in ARMAsmBackend.cpp is missing a trailing zero, which causes the emission of a coprocessor instruction rather than "mov r0, r0" as indicated in the comment. The test also checks for the wrong encoding. http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121203/157919.html git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169420 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03Use the new script to sort the includes of every file under lib.Chandler Carruth
Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-24ARM: Share applyFixup between ELF and Darwin.Benjamin Kramer
The implementations already diverged a bit, merge them back together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168542 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-01MachO: direct-to-object attribute for data-in-code markers.Jim Grosbach
The target backend can support data-in-code load commands even when the assembler doesn't, or vice-versa. Allow targets to opt-in for direct-to-object. PR13973. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164974 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-29Add LLVM support for Swift.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164899 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18When creating MCAsmBackend pass the CPU string as well. In X86AsmBackendRoman Divacky
store this and use it to not emit long nops when the CPU is geode which doesnt support them. Fixes PR11212. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164132 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bitsKevin Enderby
for the assembler and disassembler. Which were not being set/read correctly for offsets greater than 22 bits in some cases. Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156118 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-30ARM: Diagnostics for out of range fixups.Jim Grosbach
Replace some assert() calls w/ actual diagnostics. In a perfect world, there'd be range checks on these values long before things ever reached this code. For now, though, issuing a better-late-than-never diagnostic is still a big improvement over assert(). rdar://11347287 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155851 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26ARM: Thumb ldr(literal) base address alignment is 32-bits.Jim Grosbach
The base address for the PC-relative load is Align(PC,4), so it's the address of the word containing the 16-bit instruction, not the address of the instruction itself. Ugh. rdar://11314619 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155659 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-12ARM 'adr' fixups don't need the interworking addend tweaking.Jim Grosbach
They reference the PC directly, so things work properly that way. rdar://11231229 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154576 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30ARM fix encoding fixup resolution for ldrd and friends.Jim Grosbach
The 8-bit payload is not contiguous in the opcode. Move the upper nibble over 4 bits into the correct place. rdar://11158641 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153780 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30Ensure conditional BL instructions for ARM are given the fixup ↵James Molloy
fixup_arm_condbranch. Patch by Tim Northover! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153737 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27Prune some includesCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153502 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-26Prune some includes and forward declarations.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153429 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19ARM branch relaxation for unconditional t1 branches.Jim Grosbach
rdar://11059157 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153055 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27ARM BL/BLX instruction fixups should use relocations.Jim Grosbach
We on the linker to resolve calls to the appropriate BL/BLX instruction to make interworking function correctly. It uses the symbol in the relocation to do that, so we need to be careful about being too clever. To enable this for ARM mode, split the BL/BLX fixup kind off from the unconditional-branch fixups. rdar://10927209 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151571 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19Silence warnings about mixing enums.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148495 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19Thumb2 relaxation for tADR to t2ADR.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148456 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19Add comment and fix range check in condition.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148455 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Thumb2 relaxation for LDR(literal).Jim Grosbach
If the fixup is out of range for the Thumb1 instruction, relax it to the Thumb2 encoding instead. rdar://10711829 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148424 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Tidy up. MCAsmBackend naming conventions.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148400 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Thumb2 load/store fixups don't set the thumb bit.Jim Grosbach
Load/store instructions w/ a fixup to be relative a function marked as thumb don't use the low bit to specify thumb vs. non-thumb like interworking branches do, so don't set it when dealing with those fixups. rdar://10348687. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148366 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Move some ARM specific MCAssmebler bits into the ARMAsmBackend.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148364 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22Move the ARM specific parts of the ELF writer to Target/ARM.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147115 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21Reduce the exposure of Triple::OSType in the ELF object writer. This willRafael Espindola
avoid including ADT/Triple.h in many places when the target specific bits are moved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19ARM assembly parsing and encoding support for LDRD(label).Jim Grosbach
rdar://9932658 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06Tidy up value checking.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06Fix ARM handling of tBcc branch relaxation.Jim Grosbach
rdar://10069056 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145885 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06Move target-specific logic out of generic MCAssembler.Jim Grosbach
Whether a fixup needs relaxation for the associated instruction is a target-specific function, as the FIXME indicated. Create a hook for that and use it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145881 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05Simple branch relaxation for Thumb2 Bcc instructions.Jim Grosbach
Not right yet, as the rules for when to relax in the MCAssembler aren't (yet) correct for ARM. This is a step in the proper direction, though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145871 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16Generalize the fixup info for ARM mode.Jim Grosbach
We don't (yet) have the granularity in the fixups to be specific about which bitranges are affected. That's a future cleanup, but we're not there yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144852 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16Fix encoding of NOP used for padding in ARM mode .align.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144842 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-01ARM VLD/VST assembly parsing for symbolic address operands.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143413 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30Correct for my over-eager delete finger.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140892 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30ARM Fixup valus for movt/movw are for the whole value.Jim Grosbach
Remove an assert that was expecting only the relevant 16bit portion for the fixup being handled. Also kill some dead code in the T2 portion. rdar://9653509 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140861 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24ARM asm backend initialize isThumbMode based on target triple.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138501 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19Thumb assembly parsing and encoding for LDR(literal).Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138052 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18ARM Thumb blx instruction fixup has same data range as bl.Jim Grosbach
These fixups are handled poorly in general, and should have a single contiguous range of bits per fixup type, but that's not how they're currently organized, so for now in complex ones like for blx, we just tell the emitter it's OK for the fixup to munge any bit it wants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137947 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-16ARM .align NOP padding uses different encoding pre-ARMv6.Jim Grosbach
Patch by Kristof Beyls and James Malloy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137723 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to ↵Evan Cheng
createMCAsmBackend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136010 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-23Move TargetAsmParser.h TargetAsmBackend.h and TargetAsmLexer.h to MC where ↵Evan Cheng
they belong. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135833 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-23Sink ARM mc routines into MCTargetDesc.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135825 91177308-0d34-0410-b5e6-96231b3b80d8
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