| Age | Commit message (Expand) | Author |
|---|
| 2010-11-16 | Encode the multi-load/store instructions with their respective modes ('ia', | Bill Wendling |
| 2010-11-03 | Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536. | Evan Cheng |
| 2010-11-03 | Break ARM addrmode4 (load/store multiple base address) into its constituent | Jim Grosbach |
| 2010-10-28 | PLD, PLDW, PLI encodings, plus refactor their use of addrmode2. | Jim Grosbach |
| 2010-10-13 | Detabify and clean up 80 column violations. | Jim Grosbach |
| 2010-10-13 | Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern | Jim Grosbach |
| 2010-10-11 | MSVC hangs on compilation of ARMDisassembler.cpp. PR6866 applied to ARM target. | Francois Pichet |
| 2010-09-28 | Add ARM Disassembler to the CMake build. | Oscar Fuentes |
| 2010-09-17 | Fix vmov.f64 disassembly on targets where sizeof(long) != 8. | Benjamin Kramer |
| 2010-09-16 | store MC FP immediates as a double instead of as an APFloat, thus avoiding an | Jim Grosbach |
| 2010-09-15 | Teach the MC disassembler to handle vmov.f32 and vmov.f64 immediate to register | Jim Grosbach |
| 2010-09-14 | Reapply r113875 with additional cleanups. | Jim Grosbach |
| 2010-09-08 | ARM/Disassembler: Fix definitions incompatible(unsigned and uint32_t) to Cygw... | NAKAMURA Takumi |
| 2010-09-07 | hopefully fix a problem building on cygwin-1.5 | Chris Lattner |
| 2010-08-27 | Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like | Bob Wilson |
| 2010-08-17 | explicitly handle no-op cases for clarity. Fixes clang warning. | Jim Grosbach |
| 2010-08-17 | Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid | Bob Wilson |
| 2010-08-13 | Move the Thumb2 SSAT and USAT optional shift operator out of the | Bob Wilson |
| 2010-08-13 | Refactor the code for disassembling Thumb2 saturate instructions along the | Bob Wilson |
| 2010-08-12 | Cleaned up the for-disassembly-only entries in the arm instruction table so that | Johnny Chen |
| 2010-08-12 | The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td | Johnny Chen |
| 2010-08-11 | Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm. | Johnny Chen |
| 2010-08-11 | Move the ARM SSAT and USAT optional shift amount operand out of the | Bob Wilson |
| 2010-08-11 | - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the | Evan Cheng |
| 2010-08-11 | Add a separate ARM instruction format for Saturate instructions. | Bob Wilson |
| 2010-07-31 | Add support for disassembling VMVN (immediate) instructions. PR7747. | Bob Wilson |
| 2010-07-30 | Add a check in the ARM disassembler for NEON instructions that would | Bob Wilson |
| 2010-07-30 | Many Thumb2 instructions can reference the full ARM register set (i.e., | Jim Grosbach |
| 2010-07-29 | Don't assert on an unrecognized BrMiscFrm instruction. | Bob Wilson |
| 2010-07-20 | prune #includes a little. | Chris Lattner |
| 2010-07-16 | Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction | Jim Grosbach |
| 2010-07-12 | Convert some tab stops into spaces. | Duncan Sands |
| 2010-06-26 | Renumber NEON instruction formats to be consecutive. | Bob Wilson |
| 2010-06-25 | Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm to | Bob Wilson |
| 2010-06-25 | Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats. | Bob Wilson |
| 2010-06-19 | Silence compiler warnings. | Dan Gohman |
| 2010-06-18 | Start TargetRegisterClass indices at 0 instead of 1, so that | Dan Gohman |
| 2010-06-11 | Add instruction encoding for the Neon VMOV immediate instruction. This changes | Bob Wilson |
| 2010-06-08 | Reapply r105521, this time appending "LLU" to 64 bit | Bruno Cardoso Lopes |
| 2010-06-05 | revert r105521, which is breaking the buildbots with stuff like this: | Chris Lattner |
| 2010-06-05 | Initial AVX support for some instructions. No patterns matched | Bruno Cardoso Lopes |
| 2010-04-21 | Modified some assert() msg strings; no other functionality change. | Johnny Chen |
| 2010-04-21 | Thumb instructions which have reglist operands at the end and predicate operands | Johnny Chen |
| 2010-04-20 | Better error-handling of getBitFieldInvMask() where msb < lsb (encoding error), | Johnny Chen |
| 2010-04-20 | For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='11... | Johnny Chen |
| 2010-04-20 | Better error-handling for DisassembleThumb2DPModImm() with 2-reg operands where | Johnny Chen |
| 2010-04-20 | More IT instruction error-handling improvements from fuzzing. | Johnny Chen |
| 2010-04-19 | Better error handling of invalid IT mask '0000', instead of just asserting. | Johnny Chen |
| 2010-04-19 | According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1 | Johnny Chen |
| 2010-04-19 | Better error-handling for DisassembleThumb2DPSoReg() where the 3-reg operand | Johnny Chen |
