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2010-11-30s/ARM::BRIND/ARM::BX/g to coincide with r120366.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120371 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29Pseudo-ize Thumb2 jump tables with explicit MC lowering to the rawJim Grosbach
instructions. This simplifies instruction printing and disassembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120333 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-16Encode the multi-load/store instructions with their respective modes ('ia',Bill Wendling
'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119310 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03Break ARM addrmode4 (load/store multiple base address) into its constituentJim Grosbach
parts. Represent the operation mode as an optional operand instead. rdar://8614429 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118137 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117571 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13Detabify and clean up 80 column violations.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116454 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13Refactor the ARM 'setend' instruction pattern. Use a single instruction patternJim Grosbach
and handle the operand explicitly. Flesh out encoding information. Add an explicit disassembler testcase for the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116432 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17Fix vmov.f64 disassembly on targets where sizeof(long) != 8.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114240 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16store MC FP immediates as a double instead of as an APFloat, thus avoiding anJim Grosbach
unnecessary dtor for MCOperand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15Teach the MC disassembler to handle vmov.f32 and vmov.f64 immediate to registerJim Grosbach
moves. Previously, the immediate was printed as the encoded integer value, which is incorrect. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14Reapply r113875 with additional cleanups.Jim Grosbach
"The register specified for a dregpair is the corresponding Q register, so to get the pair, we need to look up the sub-regs based on the qreg. Create a lookup function since we don't have access to TargetRegisterInfo here to be able to use getSubReg(ARM::dsub_[01])." Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use the dregpair modifier for the 2xdreg versions. Explicitly specifying the two registers as operands is more correct and more consistent with the other instruction patterns. This enables further cleanup of special case code in the disassembler as a nice side-effect. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just likeBob Wilson
all the other LDM/STM instructions. This fixes asm printer crashes when compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run with -O0 to check this in the future. Prior to this change VLDM/VSTM used addressing mode #5, but not really. The offset field was used to hold a count of the number of registers being loaded or stored, and the AM5 opcode field was expanded to specify the IA or DB mode, instead of the standard ADD/SUB specifier. Much of the backend was not aware of these special cases. The crashes occured when rewriting a frameindex caused the AM5 offset field to be changed so that it did not have a valid submode. I don't know exactly what changed to expose this now. Maybe we've never done much with -O0 and NEON. Regardless, there's no longer any reason to keep a count of the VLDM/VSTM registers, so we can use addressing mode #4 and clean things up in a lot of places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112322 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17explicitly handle no-op cases for clarity. Fixes clang warning.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111260 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoidBob Wilson
printing "lsl #0". This fixes the remaining parts of pr7792. Make corresponding changes for encoding/decoding these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111251 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12Cleaned up the for-disassembly-only entries in the arm instruction table so thatJohnny Chen
the memory barrier variants (other than 'SY' full system domain read and write) are treated as one instruction with option operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .tdJohnny Chen
entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2. Recover by looking for ARM:USAT encoding pattern before delegating to the auto- gened decoder. Added a "usat" test case to arm-tests.txt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110894 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm.Johnny Chen
Added two test cases to arm-tests.txt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110880 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Move the ARM SSAT and USAT optional shift amount operand out of theBob Wilson
instruction opcode. This also fixes part of PR7792. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11- Add subtarget feature -mattr=+db which determine whether an ARM cpu has theEvan Cheng
memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Add a separate ARM instruction format for Saturate instructions.Bob Wilson
(I discovered 2 more copies of the ARM instruction format list, bringing the total to 4!! Two of them were already out of sync. I haven't yet gotten into the disassembler enough to know the best way to fix this, but something needs to be done.) Add support for encoding these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-31Add support for disassembling VMVN (immediate) instructions. PR7747.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109946 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30Add a check in the ARM disassembler for NEON instructions that wouldBob Wilson
reference registers past the end of the NEON register file, and report them as invalid instead of asserting when trying to print them. PR7746. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109933 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30Many Thumb2 instructions can reference the full ARM register set (i.e.,Jim Grosbach
have 4 bits per register in the operand encoding), but have undefined behavior when the operand value is 13 or 15 (SP and PC, respectively). The trivial coalescer in linear scan sometimes will merge a copy from SP into a subsequent instruction which uses the copy, and if that instruction cannot legally reference SP, we get bad code such as: mls r0,r9,r0,sp instead of: mov r2, sp mls r0, r9, r0, r2 This patch adds a new register class for use by Thumb2 that excludes the problematic registers (SP and PC) and is used instead of GPR for those operands which cannot legally reference PC or SP. The trivial coalescer explicitly requires that the register class of the destination for the COPY instruction contain the source register for the COPY to be considered for coalescing. This prevents errant instructions like that above. PR7499 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-29Don't assert on an unrecognized BrMiscFrm instruction.Bob Wilson
PR7745. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109788 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instructionJim Grosbach
and a combine pattern to use it for setting a bit-field to a constant value. More to come for non-constant stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12Convert some tab stops into spaces.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108130 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-26Renumber NEON instruction formats to be consecutive.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106927 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm toBob Wilson
"N..." instead of "NEON..." for consistency with the other NEON format names. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106921 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats.Bob Wilson
Renumber MiscFrm to 25. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106916 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19Silence compiler warnings.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18Start TargetRegisterClass indices at 0 instead of 1, so thatDan Gohman
MachineRegisterInfo doesn't have to confusingly allocate an extra entry. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-11Add instruction encoding for the Neon VMOV immediate instruction. This changesBob Wilson
the machine instruction representation of the immediate value to be encoded into an integer with similar fields as the actual VMOV instruction. This makes things easier for the disassembler, since it can just stuff the bits into the immediate operand, but harder for the asm printer since it has to decode the value to be printed. Testcase for the encoding will follow later when MC has more support for ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105836 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21Thumb instructions which have reglist operands at the end and predicate operandsJohnny Chen
before reglist were not properly handled with respect to IT Block. Fix that by creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those instructions for disassembly. Add a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101974 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19Better error handling of invalid IT mask '0000', instead of just asserting.Johnny Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101827 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1Johnny Chen
Pseudocode details of conditional, Condition bits '111x' indicate the instruction is always executed. That is, '1111' is a leagl condition field value, which is now mapped to ARMCC::AL. Also add a test case for condition field '1111'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101817 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19ARM disassembler did not react to recent changes to the NEON instruction table.Johnny Chen
VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101784 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16Cast to (uint64_t) instead of relying on the "ul" suffix.Johnny Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for aJohnny Chen
case. Also, the 0xFF hex literal involved in the shift for ESize64 should be suffixed "ul" to preserve the shift result. Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101557 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15DEBUG() print out "Unknown format" msg.Johnny Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101382 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15Wrap the error msgs in DEBUG() macro so that they won't appear in NDEBUG build.Johnny Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101329 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14Fixed another assert exposed by fuzzing. Now, the DisassembleVFPLdStMulFrm()Johnny Chen
function checks whether we have a valid submode for VLDM/VSTM (must be either "ia" or "db") before calling ARM_AM::getAM5Opc(AMSubMode, unsigned char). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101306 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14For t2BFI disassembly, apply the same error checking as in r101205.Johnny Chen
Change the error msg to read "Encoding error: msb < lsb". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101293 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14Fixed another assert exposed by fuzzing. The utility function getRegisterEnum()Johnny Chen
was asserting because the (RegClass, RegNum) combination doesn't make sense from an encoding point of view. Since getRegisterEnum() is used all over the place, to change the code to check for encoding error after each call would not only bloat the code, but also make it less readable. An Err flag is added to the ARMBasicMCBuilder where a client can set a non-zero value to indicate some kind of error condition while building up the MCInst. ARMBasicMCBuilder::BuildIt() checks this flag and returns false if a non-zero value is detected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101290 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14Fixed another assert exposed by fuzzing. Now, when an encoding error occursJohnny Chen
involing getBFCInvMask() where lsb <= msb does not hold true, the disassembler just returns false, instead of assert, to indicate disassembly error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101205 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14Fixed an assert() exposed by fuzzing. Now, instead of assert when an invalidJohnny Chen
instruction encoding is encountered, we just return a NULL ARMBasicMCBuilder instance and the client just returns false to indicate disassembly error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07Missed this one line for the previous checkin to fix build warnings.Johnny Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100697 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07Fixed warnings pointed out by clang.Johnny Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100696 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07Fixed 3 warnings pointed out by clang.Johnny Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100693 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-05Re-apply 100265 but instead disable building of ARM disassembly for now.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100379 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-05Reverting 100265 to try to get buildbots green again. Lots of self-hosting ↵Evan Cheng
buildbots started complaining since this commit. Also xfail ARM disassembly tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100378 91177308-0d34-0410-b5e6-96231b3b80d8
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