| Age | Commit message (Expand) | Author |
|---|
| 2011-10-24 | Fix a NEON disassembly case that was broken in the recent refactorings. As m... | Owen Anderson |
| 2011-10-22 | Move various generated tables into read-only memory, fixing up const correctn... | Benjamin Kramer |
| 2011-10-21 | Assembly parsing for 4-register sequential variant of VLD2. | Jim Grosbach |
| 2011-10-21 | Assembly parsing for 2-register sequential variant of VLD2. | Jim Grosbach |
| 2011-10-21 | Assembly parsing for 4-register variant of VLD1. | Jim Grosbach |
| 2011-10-21 | Assembly parsing for 3-register variant of VLD1. | Jim Grosbach |
| 2011-10-21 | ARM VLD parsing and encoding. | Jim Grosbach |
| 2011-10-20 | Tidy up. Trailing whitespace. | Jim Grosbach |
| 2011-10-17 | Removed set, but unused variables. | Chad Rosier |
| 2011-10-14 | Fix a non-firing assert. Change: | Richard Trieu |
| 2011-10-13 | Fix undefined shift. Patch by Ahmed Charles. | Eli Friedman |
| 2011-10-13 | SETEND is not allowed in an IT block. | Owen Anderson |
| 2011-10-12 | ARM addrmode5 represents the 'U' bit of the encoding backwards. | Jim Grosbach |
| 2011-10-12 | Thumb2 assembly parsing and encoding for LDC/STC. | Jim Grosbach |
| 2011-10-12 | addrmode2 is gone from these, so no need for the reg0 operand. | Jim Grosbach |
| 2011-10-06 | Fix the check for nested IT instructions in the disassembler. We need to per... | Owen Anderson |
| 2011-10-04 | Adding back support for printing operands symbolically to ARM's new disassembler | Kevin Enderby |
| 2011-09-30 | ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. | Jim Grosbach |
| 2011-09-26 | ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. | Owen Anderson |
| 2011-09-23 | Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid t... | Owen Anderson |
| 2011-09-23 | Revert r140412. This affects more instructions than intended. | Owen Anderson |
| 2011-09-23 | Thumb2 register-shifted-register loads cannot target the PC or the SP. | Owen Anderson |
| 2011-09-19 | tMOVSr is not allowed in an IT block either. | Owen Anderson |
| 2011-09-19 | CPS instructions are UNPREDICTABLE inside IT blocks. | Owen Anderson |
| 2011-09-19 | Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not... | Owen Anderson |
| 2011-09-19 | Thumb2 assembly parsing and encoding for TBB/TBH. | Jim Grosbach |
| 2011-09-19 | Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Por... | Owen Anderson |
| 2011-09-16 | Bitfield mask instructions are unpredictable if the encoded LSB is higher tha... | Owen Anderson |
| 2011-09-16 | Fix bitfield decoding based on Eli's feedback. | Owen Anderson |
| 2011-09-16 | Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt. | Owen Anderson |
| 2011-09-16 | Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32). | Owen Anderson |
| 2011-09-16 | Fix disassembly of Thumb2 LDRSH with a #-0 offset. | Owen Anderson |
| 2011-09-15 | Don't attach annotations to MCInst's. Instead, have the disassembler return,... | Owen Anderson |
| 2011-09-14 | Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them. | Owen Anderson |
| 2011-09-12 | Port more encoding tests to decoding tests, and correct an improper Thumb2 pr... | Owen Anderson |
| 2011-09-09 | LDM writeback is not allowed if Rn is in the target register list. | Owen Anderson |
| 2011-09-09 | Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands. | Owen Anderson |
| 2011-09-09 | Thumb unconditional branches are allowed in IT blocks, and therefore should h... | Owen Anderson |
| 2011-09-09 | Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. | Jim Grosbach |
| 2011-09-08 | All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ. | Owen Anderson |
| 2011-09-08 | Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block. | Owen Anderson |
| 2011-09-08 | Thumb2 assembly parsing and encoding for LDRD(immediate). | Jim Grosbach |
| 2011-09-08 | Remove the "common" set of instructions shared between ARM and Thumb2 modes. ... | Owen Anderson |
| 2011-09-07 | Create Thumb2 versions of STC/LDC, and reenable the relevant tests. | Owen Anderson |
| 2011-09-07 | Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds p... | James Molloy |
| 2011-09-07 | Port more assembler tests over to disassembler tests, and fix a minor logic e... | Owen Anderson |
| 2011-09-07 | Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= ... | James Molloy |
| 2011-09-01 | Merge the ARM disassembler header into the implementation file, since it is n... | Owen Anderson |
| 2011-09-01 | Fix 80 columns violations. | Owen Anderson |
| 2011-09-01 | Fix up r137380 based on post-commit review by Jim Grosbach. | James Molloy |
