| Age | Commit message (Expand) | Author |
|---|
| 2011-09-09 | Thumb unconditional branches are allowed in IT blocks, and therefore should h... | Owen Anderson |
| 2011-09-09 | Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. | Jim Grosbach |
| 2011-09-08 | All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ. | Owen Anderson |
| 2011-09-08 | Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block. | Owen Anderson |
| 2011-09-08 | Thumb2 assembly parsing and encoding for LDRD(immediate). | Jim Grosbach |
| 2011-09-08 | Remove the "common" set of instructions shared between ARM and Thumb2 modes. ... | Owen Anderson |
| 2011-09-07 | Create Thumb2 versions of STC/LDC, and reenable the relevant tests. | Owen Anderson |
| 2011-09-07 | Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds p... | James Molloy |
| 2011-09-07 | Port more assembler tests over to disassembler tests, and fix a minor logic e... | Owen Anderson |
| 2011-09-07 | Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= ... | James Molloy |
| 2011-09-01 | Merge the ARM disassembler header into the implementation file, since it is n... | Owen Anderson |
| 2011-09-01 | Fix 80 columns violations. | Owen Anderson |
| 2011-09-01 | Fix up r137380 based on post-commit review by Jim Grosbach. | James Molloy |
| 2011-08-31 | The asm parser currently selects the wrong encoding for non-conditional Thumb... | Owen Anderson |
| 2011-08-30 | Fix issues with disassembly of IT instructions involving condition codes othe... | Owen Anderson |
| 2011-08-26 | Improve encoding support for BLX with immediat eoperands, and fix a BLX decod... | Owen Anderson |
| 2011-08-26 | Spelling fail. | Owen Anderson |
| 2011-08-26 | invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We w... | Owen Anderson |
| 2011-08-26 | Update for feedback from Jim. | Owen Anderson |
| 2011-08-26 | ARMDisassembler: Always return a size, even when disassembling fails. | Benjamin Kramer |
| 2011-08-26 | Support an extension of ARM asm syntax to allow immediate operands to ADR ins... | Owen Anderson |
| 2011-08-26 | Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT i... | Owen Anderson |
| 2011-08-25 | Port over additional encoding tests to decoding tests, and fix an operand ord... | Owen Anderson |
| 2011-08-24 | Perform more thorough checking of t2IT mask parameters, which fixes all remai... | Owen Anderson |
| 2011-08-24 | Be careful not to walk off the end of the operand info list while updating VF... | Owen Anderson |
| 2011-08-24 | Move TargetRegistry and TargetSelect from Target to Support where they belong. | Evan Cheng |
| 2011-08-24 | Be stricter in enforcing IT instruction predicate values, so that we don't en... | Owen Anderson |
| 2011-08-23 | Fix decoding of Thumb2 prefetch instructions, which account for all the remai... | Owen Anderson |
| 2011-08-23 | Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same in... | Owen Anderson |
| 2011-08-22 | Reject invalid imod values in t2CPS instructions. | Owen Anderson |
| 2011-08-22 | Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming major... | Owen Anderson |
| 2011-08-22 | Fix another batch of VLD/VST decoding crashes discovered by randomized testing. | Owen Anderson |
| 2011-08-22 | Correct writeback handling of duplicating VLD instructions. Discovered by ra... | Owen Anderson |
| 2011-08-22 | Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add ... | Owen Anderson |
| 2011-08-18 | STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST fo... | Owen Anderson |
| 2011-08-18 | Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs ... | Owen Anderson |
| 2011-08-18 | Remember to fill in some operands so we can print _something_ coherent even w... | Owen Anderson |
| 2011-08-18 | Improve handling of failure and unpredictable cases for CPS, STR, and SMLA in... | Owen Anderson |
| 2011-08-17 | Tidy up. 80 columns. | Jim Grosbach |
| 2011-08-17 | ARM clean up the imm_sr operand class representation. | Jim Grosbach |
| 2011-08-17 | Be more careful in the Thumb decoder hooks to avoid walking off the end of th... | Owen Anderson |
| 2011-08-17 | Allow the MCDisassembler to return a "soft fail" status code, indicating an i... | Owen Anderson |
| 2011-08-16 | Separate out Thumb1 instructions that need an S bit operand from those that d... | Owen Anderson |
| 2011-08-15 | Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2... | Owen Anderson |
| 2011-08-15 | Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM ... | Owen Anderson |
| 2011-08-15 | Fix problems decoding the to/from-lane NEON memory instructions, and add a co... | Owen Anderson |
| 2011-08-12 | Fix some remaining issues with decoding ARM-mode memory instructions, and add... | Owen Anderson |
| 2011-08-12 | Fix decoding of ARM-mode STRH. | Owen Anderson |
| 2011-08-12 | Fix decoding of pre-indexed stores. | Owen Anderson |
| 2011-08-12 | Separate decoding for STREXD and LDREXD to make each work better. | Owen Anderson |
