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2010-10-01Rename the AsmPrinter directory to InstPrinter for those targets that haveJim Grosbach
been MC-ized for assembly printing. MSP430 is mostly so, but still has the asm printer and lowering code in the printer subdir for the moment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30Now that the pseudos that needed this are all custom lowered, we can go backJim Grosbach
to an empty PrintSpecial() git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115128 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30Nuke it from orbit. It's the only way to be sure.Jim Grosbach
(Kill the dead non-MC asm printer for the ARM target.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115127 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23nuke unused varJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114676 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22Add PrintSpecial() handling for in ARM MC instruction printer.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21Add start of support for MC instruction printer of ARM jump tables. Filling inJim Grosbach
the rest of it is next up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114500 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18PC-relative pseudo instructions are lowered and printed directly. Any encounterJim Grosbach
with one in the generic printing code is an error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114242 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17Teach the (non-MC) instruction printer to use the cannonical names for push/pop,Jim Grosbach
and shift instructions on ARM. Update the tests to match. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114230 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17Hook up verbose asm comment printing for SOImm operands in MC printerJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114215 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17trailing whitespaceJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114212 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16MC-ization of the PICLDR pseudo. Next up, adding the other variantsJim Grosbach
(PICLDRB, et. al.) and PICSTR* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114098 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16Remove support for "dregpair" operand modifier, now that it is no longer beingBob Wilson
used for anything. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114067 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16store MC FP immediates as a double instead of as an APFloat, thus avoiding anJim Grosbach
unnecessary dtor for MCOperand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15Add support for the 'lane' modifier on vdup operandsJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114030 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15Reduce dependencies in the ARM MC instruction printer.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114009 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15Add support for floating point immediates to MC instruction printing. ARMJim Grosbach
VFP instructions use it for loading some constants, so implement that handling. Not thrilled with adding a member to MCOperand, but not sure there's much of a better option that's not pretty fragile (like putting a double in the union instead and just assuming that's good enough). Suggestions welcome... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113996 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14Reapply r113875 with additional cleanups.Jim Grosbach
"The register specified for a dregpair is the corresponding Q register, so to get the pair, we need to look up the sub-regs based on the qreg. Create a lookup function since we don't have access to TargetRegisterInfo here to be able to use getSubReg(ARM::dsub_[01])." Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use the dregpair modifier for the 2xdreg versions. Explicitly specifying the two registers as operands is more correct and more consistent with the other instruction patterns. This enables further cleanup of special case code in the disassembler as a nice side-effect. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14revert 113875 momentarilly. Need to fix the MC disassembler to handle theJim Grosbach
change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113878 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14trailing whitespace cleanupJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113877 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14The register specified for a dregpair is the corresponding Q register, so toJim Grosbach
get the pair, we need to look up the sub-regs based on the qreg. Create a lookup function since we don't have access to TargetRegisterInfo here to be able to use getSubReg(ARM::dsub_[01]). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-13Revert "CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally."Michael J. Spencer
This reverts commit r113632 Conflicts: cmake/modules/AddLLVM.cmake git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113819 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113632 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just likeBob Wilson
all the other LDM/STM instructions. This fixes asm printer crashes when compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run with -O0 to check this in the future. Prior to this change VLDM/VSTM used addressing mode #5, but not really. The offset field was used to hold a count of the number of registers being loaded or stored, and the AM5 opcode field was expanded to specify the IA or DB mode, instead of the standard ADD/SUB specifier. Much of the backend was not aware of these special cases. The crashes occured when rewriting a frameindex caused the AM5 offset field to be changed so that it did not have a valid submode. I don't know exactly what changed to expose this now. Maybe we've never done much with -O0 and NEON. Regardless, there's no longer any reason to keep a count of the VLDM/VSTM registers, so we can use addressing mode #4 and clean things up in a lot of places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112322 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-16Rename sat_shift operand to shift_imm, in preparation for using it for otherBob Wilson
instructions besides saturate instructions. No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111168 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12Cleaned up the for-disassembly-only entries in the arm instruction table so thatJohnny Chen
the memory barrier variants (other than 'SY' full system domain read and write) are treated as one instruction with option operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Move the ARM SSAT and USAT optional shift amount operand out of theBob Wilson
instruction opcode. This also fixes part of PR7792. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05ARM "rrx" shift operands do not have an immediate. PR7790.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110292 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20Update CMake files.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108787 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19sink the arm implementations of ASmPrinter and MCInstLowerChris Lattner
out of the AsmPrinter directory into libarm. Now the ARM InstPrinters depend jsut on the MC stuff, not on vmcore or codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108783 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-15Split -enable-finite-only-fp-math to two options:Evan Cheng
-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108465 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14Remove restriction on NEON alignment values. Some of the NEON ld/stBob Wilson
instructions use different values (e.g., 2-byte or 4-byte alignment). Also fix ARMInstPrinter to print these alignments as bits instead of bytes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108386 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13Move NEON "modified immediate" encode/decode into ARMAddressingModes.h toBob Wilson
avoid replicated code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108227 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12Convert some tab stops into spaces.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108130 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09Print "dregpair" NEON operands with a space between them, for readability andBob Wilson
consistency with other instructions that have lists of register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107944 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06Represent NEON load/store alignments in bytes, not bits.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107701 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02Fix incorrect asm-printing of some NEON immediates. Fix weak testcase soBob Wilson
that it checks the immediate values, not just the instructions opcodes. Radar 8110263. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107487 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-11Add instruction encoding for the Neon VMOV immediate instruction. This changesBob Wilson
the machine instruction representation of the immediate value to be encoded into an integer with similar fields as the actual VMOV instruction. This makes things easier for the disassembler, since it can just stuff the bits into the immediate operand, but harder for the asm printer since it has to decode the value to be printed. Testcase for the encoding will follow later when MC has more support for ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105836 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27Use report_fatal_error, not llvm_unreachable.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104899 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104891 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27Fix some bad fall-throughs in a switch statement. Both the 'Q' and 'R' casesBob Wilson
should fall through to the 'H' case, but instead 'Q' was falling through to 'R' so that it would do the wrong thing for a big-endian ARM target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104883 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25Use enums instead of literals in the ARM backend.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enumsJakob Stoklund Olesen
from ARMRegisterInfo.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104508 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12Add support for movi32 of global values to the new (MC) asm printer.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103576 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename itDuncan Sands
to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is the opposite, for future use by dragonegg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103495 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26Handle target-specific form of DBG_VALUE in AsmPrinter.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102373 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17Add const qualifiers to TargetLoweringObjectFile usage.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for aJohnny Chen
case. Also, the 0xFF hex literal involved in the shift for ESize64 should be suffixed "ul" to preserve the shift result. Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101557 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16In the same spirit of r101524, which removed the assert() from ↵Johnny Chen
printAddrMode2OffsetOperand(), this patch removes the assert() from printAddrMode3OffsetOperand() and adds a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101529 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16Remove the assert() from printAddrMode2OffsetOperand(). "#0 and #-0" areJohnny Chen
considered legal instructions. Refs: A8.6.51 LDC, LDC2 (immediate) -- page A8-107, A8.6.58 LDR (immediate, ARM) -- page A8-121, and A8.6.194 STR (immediate, ARM) -- page A8-395. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101524 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15Add const qualifiers to CodeGen's use of LLVM IR constructs.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
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