aboutsummaryrefslogtreecommitdiff
path: root/lib/Target/ARM/AsmParser
AgeCommit message (Collapse)Author
2011-07-28PLD and PLI are not predicable in ARM mode.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136427 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28ARM assembly parsing and encoding for BLX (immediate).Jim Grosbach
Add parsing support for BLX (immediate). Since the register operand version is predicated and the label operand version is not, we have to use some special handling to get the operand list right for matching. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136406 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28ARM assembly parsing and encoding for BFC and BFI.Jim Grosbach
Add parsing support that handles converting the lsb+width source into the odd way we represent the instruction (an inverted bitfield mask). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136399 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28Revert r136295. It broke nightly testers because some parts of codegen ↵Owen Anderson
weren't aware of the changes to operand ordering. I hope to revive this sometime in the future, but it's not strictly necessary for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136362 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27Refactor and improve the encodings/decodings for addrmode3 loads, and make ↵Owen Anderson
the writeback operand always the first. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136295 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.Evan Cheng
This can happen in cases where TableGen generated asm matcher cannot check whether a register operand is in the right register class. e.g. mem operands. rdar://8204588 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136292 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27ARM assembly parsing and encoding for UMULL.Jim Grosbach
Fix parsing of the 's' suffix for the mnemonic. Add tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136277 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27ARM assembly parsing and encoding for UMLAL.Jim Grosbach
Fix parsing of the 's' suffix for the mnemonic. Add tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136274 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27ARM parsing and encoding of SBFX and UBFX.Jim Grosbach
Encode the width operand as it encodes in the instruction, which simplifies the disassembler and the encoder, by using the imm1_32 operand def. Add a diagnostic for the context-sensitive constraint that the width must be in the range [1,32-lsb]. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136264 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27ARM assembly parsing and encoding for extend instructions.Jim Grosbach
Assembly parser handling for extend instruction rotate operands. Add tests for the sign extend instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136252 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27Support .code32 and .code64 in X86 assembler.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136197 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26Fix over-zealous rename from r136095.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136132 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26ARM diagnostics for ldrexd/stredx out of order paired register operands.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136110 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26Clean up the ARM asm parser a bit.Jim Grosbach
No intendeded functional change. Just cleaning up a bit to make things more self-consistent in layout and style. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136095 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26ARM parsing and encoding for SVC instruction.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136090 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to ↵Evan Cheng
MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26Clean up a pile of hacks in our CMake build relating to TableGen.Chandler Carruth
The first problem to fix is to stop creating synthetic *Table_gen targets next to all of the LLVM libraries. These had no real effect as CMake specifies that add_custom_command(OUTPUT ...) directives (what the 'tablegen(...)' stuff expands to) are implicitly added as dependencies to all the rules in that CMakeLists.txt. These synthetic rules started to cause problems as we started more and more heavily using tablegen files from *subdirectories* of the one where they were generated. Within those directories, the set of tablegen outputs was still available and so these synthetic rules added them as dependencies of those subdirectories. However, they were no longer properly associated with the custom command to generate them. Most of the time this "just worked" because something would get to the parent directory first, and run tablegen there. Once run, the files existed and the build proceeded happily. However, as more and more subdirectories have started using this, the probability of this failing to happen has increased. Recently with the MC refactorings, it became quite common for me when touching a large enough number of targets. To add insult to injury, several of the backends *tried* to fix this by adding explicit dependencies back to the parent directory's tablegen rules, but those dependencies didn't work as expected -- they weren't forming a linear chain, they were adding another thread in the race. This patch removes these synthetic rules completely, and adds a much simpler function to declare explicitly that a collection of tablegen'ed files are referenced by other libraries. From that, we can add explicit dependencies from the smaller libraries (such as every architectures Desc library) on this and correctly form a linear sequence. All of the backends are updated to use it, sometimes replacing the existing attempt at adding a dependency, sometimes adding a previously missing dependency edge. Please let me know if this causes any problems, but it fixes a rather persistent and problematic source of build flakiness on our end. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136023 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25ARM assembly parsing and encoding for SSAT16 instruction.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136006 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25ARM assembly parsing and encoding for SSAT instruction.Jim Grosbach
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the shift operand to correctly handle the allowed shift types and immediate ranges and issue meaningful diagnostics when an illegal value or shift type is specified. Add aliases to parse an ommitted shift operand (default value of 'lsl #0'). Add tests for diagnostics and proper encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25Fix more MC layering violations.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135979 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25Fix last bits of MC layer issues. llvm-mc doesn't need to initialize ↵Evan Cheng
TargetMachine's anymore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135963 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25ARM asm operand renaming. Make things a bit more explicit.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135959 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25Make assembly parser method names more consistent.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135950 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-23Move TargetAsmParser.h TargetAsmBackend.h and TargetAsmLexer.h to MC where ↵Evan Cheng
they belong. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135833 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22ARM SSAT instruction 5-bit immediate handling.Jim Grosbach
The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield. Update the representation such that we store the operand as 0-31, allowing us to remove the encoder method and the special case handling in the disassembler. Update the assembly parser and the instruction printer accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135823 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22ARM assembly parsing and encoding updates.Jim Grosbach
Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135817 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22ARM assembly parsing and encoding of SMLAL instruction.Jim Grosbach
Fix parsing of carry-setting variant SMLALS and add tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135797 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22ARM assembly parsing and encoding for SETEND instruction.Jim Grosbach
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and for correct encodings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135776 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn ↵Owen Anderson
necessitates a lot of changes to related bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135722 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21ARM Asm parser range checking for [0,31] immediates.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135719 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21Tidy up.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135706 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, ↵Owen Anderson
allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135693 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21ARM assembly parsing and encoding for PKHBT and PKHTB instructions.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135682 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng
ARM MC code from target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20ARM assembly parsing of MUL instruction.Jim Grosbach
Correctly handle 's' bit and predication suffices. Add parsing and encoding tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135596 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19Tweak ARM assembly parsing and printing of MSR instruction.Jim Grosbach
The system register spec should be case insensitive. The preferred form for output with mask values of 4, 8, and 12 references APSR rather than CPSR. Update and tidy up tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135532 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19ARM assembly parsing for MOV (register).Jim Grosbach
Correct the handling of the 's' suffix when parsing ARM mode. It's only a truly separate opcode in Thumb. Add test cases to make sure we handle the s and condition suffices correctly, including diagnostics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135513 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19Tidy up.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135507 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19Tighten conditional for 'mov' cc_out.Jim Grosbach
Make sure we only clobber the cc_out operand if it is indeed a default non-setting operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135506 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19ARM assembly parsing for MOV (immediate).Jim Grosbach
Add range checking for the immediate operand and handle the "mov" mnemonic choosing between encodings based on the value of the immediate. Add tests for fixups, encoding choice and values, and diagnostic for out of range values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135500 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19Remove unused code.Jim Grosbach
cc_out and pred operands are added during parsing via custom C++ now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135497 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19ARM range checking for so_imm operands in assembly parsing.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135489 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19Introduce MCCodeGenInfo, which keeps information that can affect codegenEvan Cheng
(including compilation, assembly). Move relocation model Reloc::Model from TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135468 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14ARM diagnostic when 's' suffix on mnemonic that can't set flags.Jim Grosbach
For example, "mlss r0, r1, r2, r3". The MLS instruction does not have a flag-setting variant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135203 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng
registeration and creation code into XXXMCDesc libraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14Don't leak operands when putting them into a shift.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135169 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13ARM Assembler support for DMB instruction.Jim Grosbach
Flesh out the options supported for the instruction. Shuffle tests a bit and add entries for the rest of the options. Add an alias to handle the default operand of "sy". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135109 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13Range checking for CDP[2] immediates.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135092 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13Range checking for 16-bit immediates in ARM assembly.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135071 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13Improve ARM assembly parsing diagnostics a bit.Jim Grosbach
Catch potential cascading errors on a malformed so_reg operand and bail after the first error. Add some tests for the diagnostics we do want. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135055 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-06-24 19:39:08 +0000