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path: root/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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2011-08-29Add support for parsing #-0 on non-memory-operand immediate values, and add ↵Owen Anderson
a testcase that necessitates it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138739 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26ARM assembly parsing tweak for pldw.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138669 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26Thumb2 assembler parsing and encoding of IT instruction.Jim Grosbach
This handles only the handling of the IT instruction itself, not the processing and validation of the instructions in the IT block. That's next, and will include encoding tests for IT itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138665 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We ↵Owen Anderson
were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138653 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25Explicitly disallow predication in Thumb1 assembly.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138562 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24Thumb .n mnemonic qualifiers can be ignored for now.Jim Grosbach
We'll need to pay attention to them when we start getting more serious about the details of parsing thumb2 assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138500 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24Thumb parsing and encoding for SUB (SP minu immediate).Jim Grosbach
Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that form is Thumb2 only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138494 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24Thumb parsing and encoding support for ADD SP instructions.Jim Grosbach
Fix the test FIXME and add parsing support for the ADD (SP plus immediate) and ADD (SP plus register) instruction forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24Add missing explicit writeback operand to tSTMIA_UPD.Jim Grosbach
rdar://10014745 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138457 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng
These are strictly utilities for registering targets and components. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23Some refactoring so TargetRegistry.h no longer has to include any filesEvan Cheng
from MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138367 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23Thumb parsing and encoding for STM.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138345 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23Factor low reg checking into a helper function.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138344 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22Thumb parsing and encoding for SBC.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138311 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22Thumb parsing and encoding for RSB.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138308 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22Improve error checking for tPUSH and tPOP register lists.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138295 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22Thumb assemmbly parsing diagnostic improvements for LDM.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138287 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22Tighten up ARM reglist validation a bit.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138258 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19Thumb parsing and encoding support for NOP.Jim Grosbach
The irony is not lost that this is not a completely trivial patchset. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138143 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19Thumb assembly parsing and encoding for NEG.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138131 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19Be more lenient on tied operand matching for MUL.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138124 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19Thumb assembly parsing and encoding for MUL.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138108 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19Thumb assembly parsing and encoding for MOV.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138076 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19Thumb assembly parsing and encoding for LSL(immediate).Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138063 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19Thumb assembly parsing and encoding for LDRH.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138060 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19Thumb assembly parsing and encoding for LDRB.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19Thumb assembly parsing and encoding for LDR(immediate) form T2.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138050 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19Use helper function to check for low registers.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138048 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19Thumb assembly parsing and encoding for LDR(immediate) form T1.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138047 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18Thumb assembly parsing and encoding for LDM instruction.Jim Grosbach
Fix base register type and canonicallize to the "ldm" spelling rather than "ldmia." Add diagnostics for incorrect writeback token and out-of-range registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18Add missing 'break'.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137941 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17Thumb assembly parsing and encoding for B.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137891 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17Thumb assembly parsing and encoding for ASR.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137889 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17ARM clean up the imm_sr operand class representation.Jim Grosbach
Represent the operand value as it will be encoded in the instruction. This allows removing the specialized encoder and decoder methods entirely. Add an assembler match class while we're at it to lay groundwork for parsing the thumb shift instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137879 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-16Thumb ADD(immediate) parsing support.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137788 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-16Thumb parsing diagnostics for low-reg requirements on ADD and MOV.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137779 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-16Add missing exit for 'case'.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137774 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-16Thumb assembly parsing and encoding for ADD(register) instruction.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137759 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-16Move some logic into a helper function and expand the commentary.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137756 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-16ARM thumb assembly parsing for arithmetic flag setting instructions.Jim Grosbach
Thumb one requires that many arithmetic instruction forms have an 'S' suffix. For Thumb2, the whether the suffix is required or precluded depends on whether the instruction is in an IT block. Use target parser predicates to check for these sorts of context-sensitive constraints. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15MCTargetAsmParser target match predicate support.Jim Grosbach
Allow a target assembly parser to do context sensitive constraint checking on a potential instruction match. This will be used, for example, to handle Thumb2 IT block parsing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11ARM vector compare to zero instruction assembly parsing support.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137389 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11ARM load shifted register pre-index fix shift value asm parser encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137367 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11ARM STRH assembly parsing and encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137353 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11ARM STRD assembly parsing and encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137342 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11ARM STR(immediate) assembly parsing and encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137331 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11ARM push of a single register encodes as pre-indexed STR.Jim Grosbach
Per the ARM ARM, a 'push' of a single register encodes as an STR, not an STM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137318 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11ARM pop of a single register encodes as post-indexed LDR.Jim Grosbach
Per the ARM ARM, a 'pop' of a single register encodes as an LDR, not an LDM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137316 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10ARM LDRH(immediate) assembly parsing and encoding support.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137260 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10ARM LDRD(register) assembly parsing and encoding.Jim Grosbach
Add support for literal encoding of #-0 along the way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137254 91177308-0d34-0410-b5e6-96231b3b80d8
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