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path: root/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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2011-07-21ARM Asm parser range checking for [0,31] immediates.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135719 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21Tidy up.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135706 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, ↵Owen Anderson
allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135693 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21ARM assembly parsing and encoding for PKHBT and PKHTB instructions.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135682 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng
ARM MC code from target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20ARM assembly parsing of MUL instruction.Jim Grosbach
Correctly handle 's' bit and predication suffices. Add parsing and encoding tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135596 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19Tweak ARM assembly parsing and printing of MSR instruction.Jim Grosbach
The system register spec should be case insensitive. The preferred form for output with mask values of 4, 8, and 12 references APSR rather than CPSR. Update and tidy up tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135532 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19ARM assembly parsing for MOV (register).Jim Grosbach
Correct the handling of the 's' suffix when parsing ARM mode. It's only a truly separate opcode in Thumb. Add test cases to make sure we handle the s and condition suffices correctly, including diagnostics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135513 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19Tidy up.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135507 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19Tighten conditional for 'mov' cc_out.Jim Grosbach
Make sure we only clobber the cc_out operand if it is indeed a default non-setting operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135506 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19ARM assembly parsing for MOV (immediate).Jim Grosbach
Add range checking for the immediate operand and handle the "mov" mnemonic choosing between encodings based on the value of the immediate. Add tests for fixups, encoding choice and values, and diagnostic for out of range values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135500 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19Remove unused code.Jim Grosbach
cc_out and pred operands are added during parsing via custom C++ now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135497 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19ARM range checking for so_imm operands in assembly parsing.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135489 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14ARM diagnostic when 's' suffix on mnemonic that can't set flags.Jim Grosbach
For example, "mlss r0, r1, r2, r3". The MLS instruction does not have a flag-setting variant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135203 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng
registeration and creation code into XXXMCDesc libraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14Don't leak operands when putting them into a shift.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135169 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13ARM Assembler support for DMB instruction.Jim Grosbach
Flesh out the options supported for the instruction. Shuffle tests a bit and add entries for the rest of the options. Add an alias to handle the default operand of "sy". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135109 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13Range checking for CDP[2] immediates.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135092 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13Range checking for 16-bit immediates in ARM assembly.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135071 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13Improve ARM assembly parsing diagnostics a bit.Jim Grosbach
Catch potential cascading errors on a malformed so_reg operand and bail after the first error. Add some tests for the diagnostics we do want. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135055 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13Flesh out ARM Parser support for shifted-register operands.Jim Grosbach
Now works for parsing register shifted register and register shifted immediate arithmetic instructions, including the 'rrx' rotate with extend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135049 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13Update MCParsedAsmOperand debug methods.Jim Grosbach
Update the debug output interface for MCParsedAsmOperand to have a print() method which takes an output stream argument, an << operator which invokes the print method using the given stream, and a dump() method which prints the operand to the dbgs() stream. This makes the interface more consistent with the rest of LLVM, and more convenient to use at the debugger command line. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135043 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11Fix recognition of ARM 'adcs' mnemonic.Jim Grosbach
The 'CS' is not a predication suffix in this case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134903 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09Change createAsmParser to take a MCSubtargetInfo instead of triple,Evan Cheng
CPU, and feature string. Parsing some asm directives can change subtarget state (e.g. .code 16) and it must be reflected in other modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance must be shared. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134795 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08Fix indentation.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134764 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08Add support for ARM / Thumb mode switching with .code 16 and .code 32.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134760 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08Plug a leak by giving the AsmParser ownership of the MCSubtargetInfo.Benjamin Kramer
Found by valgrind. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134738 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08TargetAsmParser doesn't need reference to Target.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134721 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08Eliminate asm parser's dependency on TargetMachine:Evan Cheng
- Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134678 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30Thumb1 register to register MOV instruction is predicable.Jim Grosbach
Fix a FIXME and allow predication (in Thumb2) for the T1 register to register MOV instructions. This allows some better codegen with if-conversion (as seen in the test updates), plus it lays the groundwork for pseudo-izing the tMOVCC instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134197 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27ARM Assembly support for Thumb mov-immediate.Jim Grosbach
Correctly parse the forms of the Thumb mov-immediate instruction: 1. 8-bit immediate 0-255. 2. 12-bit shifted-immediate. The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic, but is not yet supported. More parser logic necessary there due to fixups. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133966 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27ARM Asm parsing of Thumb2 move immediate.Jim Grosbach
Thumb2 MOV mnemonic can accept both cc_out and predication. We don't (yet) encode the instruction properly, but this gets the parsing part. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133945 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Add exception necessitated by 133938.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133939 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27ARM assembly carry set/clear condition code aliases for 'hi/lo'Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133938 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27ARM asm parser wasn't able to parse a "mov" instruction while in ThumbBruno Cardoso Lopes
mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode, default to the Thumb 1 versions/encodings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132233 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25Fix PR9762Bruno Cardoso Lopes
Enable the parsing of the operand "cpsr_all" for the ARM msr instruction git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-16sets bit 0 of the function address of thumb function in .symtabRafael Espindola
("T is 1 if the target symbol S has type STT_FUNC and the symbol addresses a Thumb instruction ;it is 0 otherwise." from "ELF for the ARM Architecture" 4.7.1.2) Patch by Koan-Sin Tan! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131406 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-18Small fix to the ARM AsmParser to ensure that aSean Callanan
superclass variable is instantiated properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129713 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04- Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHTBruno Cardoso Lopes
also fix the encoding of the later. - Add a new encoding bit to describe the index mode used in AM3. - Teach printAddrMode3Operand to check by the addressing mode which index mode to print. - Testcases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128832 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01Remove unused variablesMatt Beaumont-Gay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128692 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31Apply again changes to support ARM memory asm parsing. I removedBruno Cardoso Lopes
all LDR/STR changes and left them to a future patch. Passing all checks now. - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and fix the encoding wherever is possible. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31Revert r128632 again, until I figure out what break the testsBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128635 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31Reapply r128585 without generating a lib depedency cycle. An updated log:Bruno Cardoso Lopes
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible. - Move all instructions which use am2offset without a pattern to use addrmode2. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128632 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and"Matt Beaumont-Gay
This revision introduced a dependency cycle, as nlewycky mentioned by email. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128597 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-30- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT andBruno Cardoso Lopes
{STR,LDC}{2}_PRE. - Fixed the encoding in some places. - Some of those instructions were using am2offset and now use addrmode2. Codegen isn't affected, instructions which use SelectAddrMode2Offset were not touched. - Teach printAddrMode2Operand to check by the addressing mode which index mode to print. - This is a work in progress, more work to come. The idea is to change places which use am2offset to use addrmode2 instead, as to unify assembly parser. - Add testcases for assembly parser git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128585 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24Suppress an unused variable warning in -asserts buildsMatt Beaumont-Gay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128244 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24Add asm parsing support w/ testcases for strex/ldrex family of instructionsBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128236 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18Add support to the ARM asm parser for the register-shifted-register forms of ↵Owen Anderson
basic instructions like ADD. More work left to be done to support other instances of shifter ops in the ISA. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127917 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-19Avoid dangling else warnings.Joerg Sonnenberger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-18Fix style and a typoBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125949 91177308-0d34-0410-b5e6-96231b3b80d8
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