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path: root/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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2011-08-16Thumb assembly parsing and encoding for ADD(register) instruction.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137759 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-16Move some logic into a helper function and expand the commentary.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137756 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-16ARM thumb assembly parsing for arithmetic flag setting instructions.Jim Grosbach
Thumb one requires that many arithmetic instruction forms have an 'S' suffix. For Thumb2, the whether the suffix is required or precluded depends on whether the instruction is in an IT block. Use target parser predicates to check for these sorts of context-sensitive constraints. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15MCTargetAsmParser target match predicate support.Jim Grosbach
Allow a target assembly parser to do context sensitive constraint checking on a potential instruction match. This will be used, for example, to handle Thumb2 IT block parsing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11ARM vector compare to zero instruction assembly parsing support.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137389 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11ARM load shifted register pre-index fix shift value asm parser encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137367 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11ARM STRH assembly parsing and encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137353 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11ARM STRD assembly parsing and encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137342 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11ARM STR(immediate) assembly parsing and encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137331 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11ARM push of a single register encodes as pre-indexed STR.Jim Grosbach
Per the ARM ARM, a 'push' of a single register encodes as an STR, not an STM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137318 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11ARM pop of a single register encodes as post-indexed LDR.Jim Grosbach
Per the ARM ARM, a 'pop' of a single register encodes as an LDR, not an LDM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137316 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10ARM LDRH(immediate) assembly parsing and encoding support.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137260 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10ARM LDRD(register) assembly parsing and encoding.Jim Grosbach
Add support for literal encoding of #-0 along the way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137254 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10Fix typo. Not quite sure how that slipped in there.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137245 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10ARM LDRD(immediate) assembly parsing and encoding support.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137244 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08ARM load/store label parsing.Jim Grosbach
Allow labels for load/store instructions when parsing. There's encoding issues, still, so this doesn't work all the way through, yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137064 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05ARM load instruction shifted register index operands.Jim Grosbach
Parsing and encoding for shifted index operands for load instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05ARM indexed load assembly parsing and encoding.Jim Grosbach
More parsing support for indexed loads. Fix pre-indexed with writeback parsing for register offsets and handle basic post-indexed offsets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136982 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05ARM simplify the postidx_reg operand encoding.Jim Grosbach
The immediate portion of the operand is just a boolean (the 'U' bit indicating add vs. subtract). Treat it as such. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04ARM assembly parsing and encoding for LDR instructions.Jim Grosbach
Enhance support for LDR instruction assembly parsing for post-indexed addressing with immediate values. Add tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136940 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03ARM refactoring assembly parsing of memory address operands.Jim Grosbach
Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29ARM SRS instruction parsing, diassembly and encoding support.Jim Grosbach
Fix the instruction encoding for operands. Refactor mode to use explicit instruction definitions per FIXME to be more consistent with loads/stores. Fix disassembler accordingly. Add tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136509 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29ARM assembly parsing and encoding for RFE instruction.Jim Grosbach
Fill in the missing fixed bits and the register operand bits of the instruction encoding. Refactor the definition to make the mode explicit, which is consistent with how loads and stores are normally represented and makes parsing much easier. Add parsing aliases for pseudo-instruction variants. Update the disassembler for the new representations. Add tests for parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136479 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28PLD and PLI are not predicable in ARM mode.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136427 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28ARM assembly parsing and encoding for BLX (immediate).Jim Grosbach
Add parsing support for BLX (immediate). Since the register operand version is predicated and the label operand version is not, we have to use some special handling to get the operand list right for matching. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136406 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28ARM assembly parsing and encoding for BFC and BFI.Jim Grosbach
Add parsing support that handles converting the lsb+width source into the odd way we represent the instruction (an inverted bitfield mask). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136399 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28Revert r136295. It broke nightly testers because some parts of codegen ↵Owen Anderson
weren't aware of the changes to operand ordering. I hope to revive this sometime in the future, but it's not strictly necessary for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136362 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27Refactor and improve the encodings/decodings for addrmode3 loads, and make ↵Owen Anderson
the writeback operand always the first. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136295 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.Evan Cheng
This can happen in cases where TableGen generated asm matcher cannot check whether a register operand is in the right register class. e.g. mem operands. rdar://8204588 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136292 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27ARM assembly parsing and encoding for UMULL.Jim Grosbach
Fix parsing of the 's' suffix for the mnemonic. Add tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136277 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27ARM assembly parsing and encoding for UMLAL.Jim Grosbach
Fix parsing of the 's' suffix for the mnemonic. Add tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136274 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27ARM parsing and encoding of SBFX and UBFX.Jim Grosbach
Encode the width operand as it encodes in the instruction, which simplifies the disassembler and the encoder, by using the imm1_32 operand def. Add a diagnostic for the context-sensitive constraint that the width must be in the range [1,32-lsb]. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136264 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27ARM assembly parsing and encoding for extend instructions.Jim Grosbach
Assembly parser handling for extend instruction rotate operands. Add tests for the sign extend instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136252 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27Support .code32 and .code64 in X86 assembler.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136197 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26Fix over-zealous rename from r136095.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136132 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26ARM diagnostics for ldrexd/stredx out of order paired register operands.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136110 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26Clean up the ARM asm parser a bit.Jim Grosbach
No intendeded functional change. Just cleaning up a bit to make things more self-consistent in layout and style. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136095 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26ARM parsing and encoding for SVC instruction.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136090 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to ↵Evan Cheng
MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25ARM assembly parsing and encoding for SSAT16 instruction.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136006 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25ARM assembly parsing and encoding for SSAT instruction.Jim Grosbach
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the shift operand to correctly handle the allowed shift types and immediate ranges and issue meaningful diagnostics when an illegal value or shift type is specified. Add aliases to parse an ommitted shift operand (default value of 'lsl #0'). Add tests for diagnostics and proper encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25Fix more MC layering violations.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135979 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25ARM asm operand renaming. Make things a bit more explicit.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135959 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25Make assembly parser method names more consistent.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135950 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-23Move TargetAsmParser.h TargetAsmBackend.h and TargetAsmLexer.h to MC where ↵Evan Cheng
they belong. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135833 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22ARM SSAT instruction 5-bit immediate handling.Jim Grosbach
The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield. Update the representation such that we store the operand as 0-31, allowing us to remove the encoder method and the special case handling in the disassembler. Update the assembly parser and the instruction printer accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135823 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22ARM assembly parsing and encoding updates.Jim Grosbach
Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135817 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22ARM assembly parsing and encoding of SMLAL instruction.Jim Grosbach
Fix parsing of carry-setting variant SMLALS and add tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135797 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22ARM assembly parsing and encoding for SETEND instruction.Jim Grosbach
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and for correct encodings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135776 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn ↵Owen Anderson
necessitates a lot of changes to related bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135722 91177308-0d34-0410-b5e6-96231b3b80d8
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