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path: root/lib/Target/ARM/ARMTargetMachine.cpp
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2010-06-16Make post-ra scheduling, anti-dep breaking, and register scavenger ↵Evan Cheng
(conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106091 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09Typo.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105677 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09Thumb2 IT blocks are fairly expensive. When there are multiple selects usingEvan Cheng
the same condition, it's important to make sure they are scheduled together to avoid forming multiple IT blocks. I'm adding a pre-regalloc pass that forms IT blocks early (by re-scheduling instructions and split basic blocks) to attempt to fix this. This is not turned on by default since I am not sure this is the right fix. Another issue is llvm selects are modeled as two-address conditional moves. This can be very bad when the copies before the conditional moves are not coalesced away. Teach IT formation pass to move the copies above the IT block (when legal) to avoid breaking the IT block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105669 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11Implement a bunch more TargetSelectionDAGInfo infrastructure.Dan Gohman
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and EmitTargetCodeForMemmove out of TargetLowering and into SelectionDAGInfo to exercise this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07Remove late ARM codegen optimization pass committed by accident.Anton Korobeynikov
It is not ready for public yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100673 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07Move NEON-VFP domain fixer upper, so post-RA scheduler would benefit from it.Anton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100668 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07Some initial version of global mergerAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100641 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20TargetRegistry: Fix create{AsmInfo,MCDisassembler} to return non-const objects.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99097 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-02remove dead code.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95134 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-02eliminate all the dead addSimpleCodeEmitter implementations.Chris Lattner
eliminate random "code emitter" stuff in Alpha, except for the JIT path. Next up, remove the template cruft. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95131 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-19For aligned load/store instructions, it's only required to know whether aJim Grosbach
function can support dynamic stack realignment. That's a much easier question to answer at instruction selection stage than whether the function actually will have dynamic alignment prologue. This allows the removal of the stack alignment heuristic pass, and improves code quality for cases where the heuristic would result in dynamic alignment code being generated when it was not strictly necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93885 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-02Factor the stack alignment calculations out into a target independent pass.Jim Grosbach
No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90336 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-15Detect need for autoalignment of the stack earlier to catch spills moreJim Grosbach
conservatively. eliminateFrameIndex() machinery adjust to handle addr mode 6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88874 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07indicate what the native integer types for the target are.Chris Lattner
Please verify. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86397 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-06- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relativeEvan Cheng
load of a GV from constantpool and then add pc. It allows the code sequence to be rematerializable so it would be hoisted by machine licm. - Add a late pass to break these pseudo instructions into a number of real instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm to this pass. This is done before post regalloc scheduling to allow the scheduler to proper schedule these instructions. It also allow them to be if-converted and shrunk by later passes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86304 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-06Pass StringRef by value.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86251 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-03Move subtarget check upper for NEON reg-reg fixup pass.Anton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85914 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-03Turn neon reg-reg moves fixup code into separate pass. This should reduce ↵Anton Korobeynikov
the compile time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85850 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-28Revert r85346 change to control tail merging by CodeGenOpt::Level.Bob Wilson
I'm going to redo this using the OptimizeForSize function attribute. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85426 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-27Record CodeGen optimization level in the BranchFolding pass so that we canBob Wilson
use it to control tail merging when there is a tradeoff between performance and code size. When there is only 1 instruction in the common tail, we have been merging. That can be good for code size but is a definite loss for performance. Now we will avoid tail merging in that case when the optimization level is "Aggressive", i.e., "-O3". Radar 7338114. Since the IfConversion pass invokes BranchFolding, it too needs to know the optimization level. Note that I removed the RegisterPass instantiation for IfConversion because it required a default constructor. If someone wants to keep that for some reason, we can add a default constructor with a hard-wired optimization level. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85346 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22Revert 84843. Evan, this was breaking some of the if-conversion tests.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84868 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22Move if-conversion before post-regalloc scheduling so the predicated ↵Evan Cheng
instruction get scheduled properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84843 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22Trim include.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84831 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-02Move load / store multiple before post-alloc scheduling.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83236 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30Add a option which would move ld/st multiple pass before post-alloc scheduling.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83145 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-28Pass the optimization level when constructing the ARM instruction selector.Bob Wilson
Otherwise, it is always set to "default", which prevents debug info from even being generated during isel. Radar 7250345. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82988 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-27Enable pre-regalloc load / store multiple pass for Thumb2.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82893 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-26Really remove this option.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82838 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-26Remove a couple of unused command line options.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82837 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-14trivial whitespace cleanupJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81773 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-22rename COFFMCAsmInfo -> MCAsmInfoCOFF, likewise for darwin.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79773 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-22Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79763 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15Turn on if-conversion for thumb2.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79084 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-13Revert 78892 and 78895, these break generating working executables onDaniel Dunbar
x86_64-apple-darwin10. --- Reverse-merging r78895 into '.': U test/CodeGen/PowerPC/2008-12-12-EH.ll U lib/Target/DarwinTargetAsmInfo.cpp --- Reverse-merging r78892 into '.': U include/llvm/Target/DarwinTargetAsmInfo.h U lib/Target/X86/X86TargetAsmInfo.cpp U lib/Target/X86/X86TargetAsmInfo.h U lib/Target/ARM/ARMTargetAsmInfo.h U lib/Target/ARM/ARMTargetMachine.cpp U lib/Target/ARM/ARMTargetAsmInfo.cpp U lib/Target/PowerPC/PPCTargetAsmInfo.cpp U lib/Target/PowerPC/PPCTargetAsmInfo.h U lib/Target/PowerPC/PPCTargetMachine.cpp G lib/Target/DarwinTargetAsmInfo.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78919 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-13fix a minor fixme. When building with SL and later tools, the ".eh" symbolsChris Lattner
don't need to be exported from the .o files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78892 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-12Change TargetAsmInfo to be constructed via TargetRegistry from a Target+TripleChris Lattner
pair instead of from a virtual method on TargetMachine. This cuts the final ties of TargetAsmInfo to TargetMachine, meaning that MC can now use TargetAsmInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78802 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11pass the TargetTriple down from each target ctor to theChris Lattner
LLVMTargetMachine ctor. It is currently unused. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78711 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11Whitespace cleanup. Remove trailing whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78666 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11Adding a blank line back.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78654 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch ↵Evan Cheng
of thumb2 tests to FileCheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78622 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08Add a skeleton Thumb2 instruction size reduction pass.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78456 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05Add a new pre-allocation pass to assign adjacent registers for Neon instructionsBob Wilson
that have that constraint. This is currently just assigning a fixed set of registers, and it only handles VLDn for n=2,3,4 with DPR registers. I'm going to expand it to handle more operations next; we can make it smarter once everything is working correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78256 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05Oops. I didn't mean to commit this piece yet.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78146 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05Change DAG nodes for Neon VLD2/3/4 operations to return multiple results.Bob Wilson
Get rid of yesterday's code to fix the register usage during isel. Select the new DAG nodes to machine instructions. The new pre-alloc pass to choose adjacent registers for these results is not done, so the results of this will generally not assemble yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78136 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78104 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-02Move most targets TargetMachine constructor to only taking a target triple.Daniel Dunbar
- The C, C++, MSIL, and Mips backends still need the module. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77927 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-02Normalize Subtarget constructors to take a target triple string instead ofDaniel Dunbar
Module*. Also, dropped uses of TargetMachine where unnecessary. The only target which still takes a TargetMachine& is Mips, I would appreciate it if someone would normalize this to match other targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77918 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-02ARM TAI no longer needs a TM, but createTargetAsmInfo() still does.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77878 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-27remove dead code.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77233 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-25Add new helpers for registering targets.Daniel Dunbar
- Less boilerplate == good. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77052 91177308-0d34-0410-b5e6-96231b3b80d8
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