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path: root/lib/Target/ARM/ARMScheduleA9.td
AgeCommit message (Expand)Author
2013-04-01ARM Scheduler Model: Add resources instructions, map resources in subtargetsArnold Schwaighofer
2013-03-26Revert ARM Scheduler Model: Add resources instructions, map resourcesArnold Schwaighofer
2013-03-26ARM Scheduler Model: Add resources instructions, map resources in subtargetsArnold Schwaighofer
2013-01-09MIsched: add an ILP window property to machine model.Andrew Trick
2012-09-21Cortex-A9 latency fixes (w/ -schedmodel only).Andrew Trick
2012-09-14Cortex-A9 instruction-level scheduling machine model.Andrew Trick
2012-08-08Added MispredictPenalty to SchedMachineModel.Andrew Trick
2012-07-07I'm introducing a new machine model to simultaneously allow simpleAndrew Trick
2012-07-02Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick
2012-06-29Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick
2012-06-29Make NumMicroOps a variable in the subtarget's instruction itinerary.Andrew Trick
2012-06-05ARM itinerary properties.Andrew Trick
2012-04-11Fix a number of problems with ARM fused multiply add/subtract instructions.Evan Cheng
2011-04-19Improvements for the Cortex-A9 scheduling itineraries.Bob Wilson
2011-04-19Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". ThatEvan Cheng
2011-01-20Sorry, several patches in one.Evan Cheng
2011-01-04Fix the ARM IIC_iCMPsi itinerary and add an important assert.Andrew Trick
2010-12-08Fix an obvious cut-n-paste error.Evan Cheng
2010-11-30Add support for NEON VLD3-dup instructions.Bob Wilson
2010-11-29Add support for NEON VLD3-dup instructions.Bob Wilson
2010-11-29Fix copy-and-paste errors in VLD2-dup scheduling itineraries.Bob Wilson
2010-11-28Add support for NEON VLD2-dup instructions.Bob Wilson
2010-11-27Add NEON VLD1-dup instructions (load 1 element to all lanes).Bob Wilson
2010-11-27Fix incorrect scheduling itineraries for NEON vld1/vst1 instructions.Bob Wilson
2010-11-13Conditional moves are slightly more expensive than moves.Evan Cheng
2010-11-03Fix preload instruction isel. Only v7 supports pli, and only v7 with mp exten...Evan Cheng
2010-11-03Modify scheduling itineraries to correct instruction latencies (not operandEvan Cheng
2010-11-02Add NEON VST1-lane instructions. Partial fix for Radar 8599955.Bob Wilson
2010-11-01Add NEON VLD1-lane instructions. Partial fix for Radar 8599955.Bob Wilson
2010-10-29Fix fpscr <-> GPR latency info.Evan Cheng
2010-10-28Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.Evan Cheng
2010-10-28Revert 117518 and 117519 for now. They changed scheduling and cause MC tests ...Evan Cheng
2010-10-28- Assign load / store with shifter op address modes the right itinerary classes.Evan Cheng
2010-10-21putback r116983 and fix simple-fp-encoding.ll testsAndrew Trick
2010-10-21Revert r116983, which is breaking all the buildbots.Owen Anderson
2010-10-21Add missing scheduling itineraries for transfers between core registers and V...Evan Cheng
2010-10-13Limit load / store issues (at least until we have a true multi-issue aware sc...Evan Cheng
2010-10-11More ARM scheduling itinerary fixes.Evan Cheng
2010-10-11Proper VST scheduling itineraries.Evan Cheng
2010-10-09Add VLD4 scheduling itineraries.Evan Cheng
2010-10-09Finish vld3 and vld4.Evan Cheng
2010-10-09Correct some load / store instruction itinerary mistakes:Evan Cheng
2010-10-07Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vld...Evan Cheng
2010-10-06- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. ThisEvan Cheng
2010-10-03Major changes to Cortex-A9 itinerary.Evan Cheng
2010-10-01Fix r115332: correctly model AGU / NEON mux.Evan Cheng
2010-10-01Add operand cycles for vldr / vstr.Evan Cheng
2010-10-01NEON scheduling info fix. vmov reg, reg are single cycle instructions.Evan Cheng
2010-10-01Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP iss...Evan Cheng
2010-09-30ARM instruction itinerary fixes:Evan Cheng
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