| Age | Commit message (Expand) | Author |
|---|
| 2012-08-08 | Added MispredictPenalty to SchedMachineModel. | Andrew Trick |
| 2012-07-07 | I'm introducing a new machine model to simultaneously allow simple | Andrew Trick |
| 2012-07-02 | Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary." | Andrew Trick |
| 2012-06-29 | Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary." | Andrew Trick |
| 2012-06-29 | Make NumMicroOps a variable in the subtarget's instruction itinerary. | Andrew Trick |
| 2012-06-05 | ARM itinerary properties. | Andrew Trick |
| 2012-04-11 | Fix a number of problems with ARM fused multiply add/subtract instructions. | Evan Cheng |
| 2011-01-20 | Sorry, several patches in one. | Evan Cheng |
| 2010-11-30 | Add support for NEON VLD3-dup instructions. | Bob Wilson |
| 2010-11-29 | Add support for NEON VLD3-dup instructions. | Bob Wilson |
| 2010-11-29 | Fix copy-and-paste errors in VLD2-dup scheduling itineraries. | Bob Wilson |
| 2010-11-28 | Add support for NEON VLD2-dup instructions. | Bob Wilson |
| 2010-11-27 | Add NEON VLD1-dup instructions (load 1 element to all lanes). | Bob Wilson |
| 2010-11-27 | Fix incorrect scheduling itineraries for NEON vld1/vst1 instructions. | Bob Wilson |
| 2010-11-13 | Conditional moves are slightly more expensive than moves. | Evan Cheng |
| 2010-11-03 | Fix preload instruction isel. Only v7 supports pli, and only v7 with mp exten... | Evan Cheng |
| 2010-11-03 | Modify scheduling itineraries to correct instruction latencies (not operand | Evan Cheng |
| 2010-11-02 | Add NEON VST1-lane instructions. Partial fix for Radar 8599955. | Bob Wilson |
| 2010-11-01 | Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. | Bob Wilson |
| 2010-10-29 | Fix fpscr <-> GPR latency info. | Evan Cheng |
| 2010-10-21 | putback r116983 and fix simple-fp-encoding.ll tests | Andrew Trick |
| 2010-10-21 | Revert r116983, which is breaking all the buildbots. | Owen Anderson |
| 2010-10-21 | Add missing scheduling itineraries for transfers between core registers and V... | Evan Cheng |
| 2010-10-11 | More ARM scheduling itinerary fixes. | Evan Cheng |
| 2010-10-11 | Proper VST scheduling itineraries. | Evan Cheng |
| 2010-10-09 | Add VLD4 scheduling itineraries. | Evan Cheng |
| 2010-10-09 | Finish vld3 and vld4. | Evan Cheng |
| 2010-10-09 | Complete vld2 instruction itineries. | Evan Cheng |
| 2010-10-09 | Multiply instructions are issued on pipeline 0. They do not need to reserve p... | Evan Cheng |
| 2010-10-09 | Correct some load / store instruction itinerary mistakes: | Evan Cheng |
| 2010-10-07 | Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vld... | Evan Cheng |
| 2010-10-06 | - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This | Evan Cheng |
| 2010-10-01 | Fix scheduling infor for vmovn and vshrn which I broke accidentially. | Evan Cheng |
| 2010-10-01 | Add operand cycles for vldr / vstr. | Evan Cheng |
| 2010-10-01 | NEON scheduling info fix. vmov reg, reg are single cycle instructions. | Evan Cheng |
| 2010-09-30 | ARM instruction itinerary fixes: | Evan Cheng |
| 2010-09-29 | Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP | Evan Cheng |
| 2010-09-29 | Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn. | Evan Cheng |
| 2010-09-29 | Assign bitwise binary instructions different itinerary classes from ALU instr... | Evan Cheng |
| 2010-09-28 | Add support to model pipeline bypass / forwarding. | Evan Cheng |
| 2010-09-25 | Remove a unused instruction itinerary class. | Evan Cheng |
| 2010-09-25 | Fix zero and sign extension instructions scheduling itineraries. | Evan Cheng |
| 2010-09-24 | More pseudo instruction scheduling itinerary fixes. | Evan Cheng |
| 2010-09-24 | Fix scheduling itinerary for pseudo mov immediate instructions which expand i... | Evan Cheng |
| 2010-09-08 | Fix LDM_RET schedule itinery. | Evan Cheng |
| 2010-06-28 | minor housekeeping cleanup: 80-column, trailing whitespace, spelling, etc.. N... | Jim Grosbach |
| 2010-04-18 | Make processor FUs unique for given itinerary. This extends the limit of 32 | Anton Korobeynikov |
| 2010-04-07 | Split A8/A9 itins - they already were too big. | Anton Korobeynikov |
