| Age | Commit message (Expand) | Author |
|---|
| 2012-07-02 | Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary." | Andrew Trick |
| 2012-06-29 | Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary." | Andrew Trick |
| 2012-06-29 | Make NumMicroOps a variable in the subtarget's instruction itinerary. | Andrew Trick |
| 2012-06-22 | Use "NoItineraries" for processors with no itineraries. | Andrew Trick |
| 2012-02-18 | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu |
| 2012-01-22 | Add fused multiple+add instructions from VFPv4. | Anton Korobeynikov |
| 2011-01-20 | Sorry, several patches in one. | Evan Cheng |
| 2010-11-30 | Add support for NEON VLD3-dup instructions. | Bob Wilson |
| 2010-11-29 | Add support for NEON VLD3-dup instructions. | Bob Wilson |
| 2010-11-28 | Add support for NEON VLD2-dup instructions. | Bob Wilson |
| 2010-11-27 | Add NEON VLD1-dup instructions (load 1 element to all lanes). | Bob Wilson |
| 2010-11-13 | Conditional moves are slightly more expensive than moves. | Evan Cheng |
| 2010-11-03 | Fix preload instruction isel. Only v7 supports pli, and only v7 with mp exten... | Evan Cheng |
| 2010-11-02 | Add NEON VST1-lane instructions. Partial fix for Radar 8599955. | Bob Wilson |
| 2010-11-01 | Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. | Bob Wilson |
| 2010-10-11 | More ARM scheduling itinerary fixes. | Evan Cheng |
| 2010-10-11 | Proper VST scheduling itineraries. | Evan Cheng |
| 2010-10-09 | Add VLD4 scheduling itineraries. | Evan Cheng |
| 2010-10-09 | Finish vld3 and vld4. | Evan Cheng |
| 2010-10-09 | Correct some load / store instruction itinerary mistakes: | Evan Cheng |
| 2010-10-07 | Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vld... | Evan Cheng |
| 2010-10-06 | - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This | Evan Cheng |
| 2010-10-01 | NEON scheduling info fix. vmov reg, reg are single cycle instructions. | Evan Cheng |
| 2010-09-30 | ARM instruction itinerary fixes: | Evan Cheng |
| 2010-09-29 | Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP | Evan Cheng |
| 2010-09-29 | Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn. | Evan Cheng |
| 2010-09-29 | Assign bitwise binary instructions different itinerary classes from ALU instr... | Evan Cheng |
| 2010-09-28 | Add support to model pipeline bypass / forwarding. | Evan Cheng |
| 2010-09-25 | Remove a unused instruction itinerary class. | Evan Cheng |
| 2010-09-25 | Fix zero and sign extension instructions scheduling itineraries. | Evan Cheng |
| 2010-09-24 | More pseudo instruction scheduling itinerary fixes. | Evan Cheng |
| 2010-09-24 | Fix scheduling itinerary for pseudo mov immediate instructions which expand i... | Evan Cheng |
| 2010-09-09 | For each instruction itinerary class, specify the number of micro-ops each | Evan Cheng |
| 2010-09-08 | Fix LDM_RET schedule itinery. | Evan Cheng |
| 2010-04-18 | Make processor FUs unique for given itinerary. This extends the limit of 32 | Anton Korobeynikov |
| 2010-04-07 | Split A8/A9 itins - they already were too big. | Anton Korobeynikov |
| 2010-04-07 | Fix itins for VABA | Anton Korobeynikov |
| 2010-04-07 | VHADD differs from VHSUB at least on A9 - the former reads both operands in t... | Anton Korobeynikov |
| 2010-04-07 | Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON op... | Anton Korobeynikov |
| 2010-04-07 | Add new itin classes for FP16 <-> FP32 conversions and make uise of them for A9. | Anton Korobeynikov |
| 2010-04-07 | Make use of new reserved/required scheduling stuff: introduce VFP and NEON lo... | Anton Korobeynikov |
| 2009-09-25 | Finish scheduling itineraries for NEON. | David Goodwin |
| 2009-09-24 | Make the end-of-itinerary mark explicit. Some cleanup. | David Goodwin |
| 2009-09-23 | Checkpoint NEON scheduling itineraries. | David Goodwin |
| 2009-09-21 | Add Cortex-A8 VFP model. | David Goodwin |
| 2009-08-19 | Update Cortex-A8 instruction itineraries for integer instructions. | David Goodwin |
| 2009-08-15 | Turn on if-conversion for thumb2. | Evan Cheng |
| 2009-08-13 | Finalize itineraries for cortex-a8 integer multiply | David Goodwin |
| 2009-08-11 | Allow a zero cycle stage to reserve/require a FU without advancing the cycle ... | David Goodwin |
| 2009-08-10 | Checkpoint scheduling itinerary changes. | David Goodwin |
