aboutsummaryrefslogtreecommitdiff
path: root/lib/Target/ARM/ARMISelLowering.cpp
AgeCommit message (Collapse)Author
2010-02-18Use NEON vmin/vmax instructions for floating-point selects.Bob Wilson
Radar 7461718. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96572 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-15Remove an assumption of default arguments. This is in anticipation of aDavid Greene
change to SelectionDAG build APIs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96230 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-08tighten up eh.setjmp sequence a bit.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95603 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-02Revert 95130.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95160 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-02Pass callsite return type to TargetLowering::LowerCall and use that to check ↵Evan Cheng
sibcall eligibility. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95130 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-30Fix a gross typo: ARMv6+ may or may not support unaligned memory operations.Anton Korobeynikov
Even if they are suported by the core, they can be disabled (this is just a configuration bit inside some register). Allow unaligned memops on darwin and conservatively disallow them otherwise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94889 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-27Eliminate target hook IsEligibleForTailCallOptimization.Evan Cheng
Target independent isel should always pass along the "tail call" property. Change target hook LowerCall's parameter "isTailCall" into a refernce. If the target decides it's impossible to honor the tail call request, it should set isTailCall to false to make target independent isel happy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94626 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-19Wrap some comments to 80 columns.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93940 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-18Patch by David Conrad:Jim Grosbach
"On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction sequence it is now." git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93758 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-15Name change for consistency. No functional change.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93480 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-15EmitAtomicCmpSwap() custome inserter needs to delete the MI passed in. ↵Jim Grosbach
EmitAtomicBinary() already does this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93479 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-14ARM "l" constraint for inline asm means R0-R7, also for Thumb2.Jakob Stoklund Olesen
This is consistent with llvm-gcc's arm/constraints.md. Certain instructions (e.g. CBZ, CBNZ) require a low register, even in Thumb2 mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93436 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-13Fix pastoJakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93342 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22Add more plumbing. This time in the LowerArguments and "get" functions whichBill Wendling
return partial registers. This affected the back-end lowering code some. Also patch up some places I missed before in the "get" functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91880 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-21Delete the instruction just before the function terminates for consistency sake.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91836 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18Fix libstdc++ build on ARM linux and part of PR5770.Rafael Espindola
MI was not being used but it was also not being deleted, so it was kept in the garbage list. The memory itself was freed once the function code gen was done. Once in a while the codegen of another function would create an instruction on the same address. Adding it to the garbage group would work once, but when another pointer was added it would cause an assert as "Cache" was about to be pushed to Ts. For a patch that make us detect problems like this earlier, take a look at http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20091214/092758.html With that patch we assert as soon and the new instruction is added to the garbage set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91691 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18Handle ARM inline asm "w" constraints with 64-bit ("d") registers.Bob Wilson
The change in SelectionDAGBuilder is needed to allow using bitcasts to convert between f64 (the default type for ARM "d" registers) and 64-bit Neon vector types. Radar 7457110. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91649 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-15nand atomic requires opposite operand orderingJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91371 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-14Add ARMv6 memory and sync barrier instructionsJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91329 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-14Thumb2 atomic operationsJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91321 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-14atomic binary operations up to 32-bits wide.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91260 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-12Framework for atomic binary operations. The emitter for the pseudo instructionsJim Grosbach
just issues an error for the moment. The front end won't yet generate these intrinsics for ARM, so this is behind the scenes until complete. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91200 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-11Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in ↵Jim Grosbach
progress. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91090 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-10Add memory barrier intrinsic support for ARM. Moving towards adding the ↵Jim Grosbach
atomic operations intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91003 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-08- Support inline asm 'w' constraint for 128-bit vector types.Evan Cheng
- Also support the 'q' NEON registers asm code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90894 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-03Recognize canonical forms of vector shuffles where the same vector is used forBob Wilson
both source operands. In the canonical form, the 2nd operand is changed to an undef and the shuffle mask is adjusted to only reference elements from the 1st operand. Radar 7434842. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90417 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-24Materialize global addresses via movt/movw pair, this is always betterAnton Korobeynikov
than doing the same via constpool: 1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2. 2. Load from constpool might stall up to 300 cycles due to cache miss. 3. Movt/movw does not use load/store unit. 4. Less constpool entries => better compiler performance. This is only enabled on ELF systems, since darwin does not have needed relocations (yet). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89720 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-23Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.Dan Gohman
Note that "hasDotLocAndDotFile"-style debug info was already broken; people wanting this functionality should implement it in the AsmPrinter/DwarfWriter code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89711 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-21We are not using DBG_STOPPOINT anymore.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89536 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12Add a bool flag to StackObjects telling whether they reference spillDavid Greene
slots. The AsmPrinter will use this information to determine whether to print a spill/reload comment. Remove default argument values. It's too easy to pass a wrong argument value when multiple arguments have default values. Make everything explicit to trap bugs early. Update all targets to adhere to the new interfaces.. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87022 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12isLegalICmpImmediate should take a signed integer; code clean up.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86964 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-11Add TargetLowering::isLegalICmpImmediate. It tells LSR what immediate can be ↵Evan Cheng
folded into target icmp instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86858 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-09Use Unified Assembly Syntax for the ARM backend.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-06Remove ARMPCLabelIndex from ARMISelLowering. Use ↵Evan Cheng
ARMFunctionInfo::createConstPoolEntryUId() instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86294 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-03Revert previous change to a comment. The BlockAddresses go in theBob Wilson
constant pool so they don't get wrapped separately. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85844 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-02Put BlockAddresses into ARM constant pools.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85824 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-02Handle splats of undefs properly. This includes the testcase for PR5364 as well.Anton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85767 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31Expand 64-bit logical shift right inlineJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85687 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31Expand 64-bit arithmetic shift right inlineJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85685 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31Expand 64 bit left shift inline rather than using the libcall. For now, thisJim Grosbach
is unconditional. Making it still use the libcall when optimizing for size would be a good adjustment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85675 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to ↵Evan Cheng
enable more machine licm. More changes coming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85643 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-30Fix a comment.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85610 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-30This fixes functions likeRafael Espindola
void f (int a1, int a2, int a3, int a4, int a5,...) In ARMTargetLowering::LowerFormalArguments if the function has 4 or more regular arguments we used to set VarArgsFrameIndex using an offset of 0, which is only correct if the function has exactly 4 regular arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85590 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-30Add ARM codegen for indirect branches.Bob Wilson
clang/test/CodeGen/indirect-goto.c runs! (unoptimized) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85577 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-28Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85381 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-28Use fconsts and fconstd to materialize small fp constants.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85362 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21Most of the NEON shuffle instructions do not support 64-bit element types.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84785 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21Match more patterns to movt.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84751 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20Random #include pruning.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84632 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-15Revert svn r80498 and replace it with a different solution. The only problemBob Wilson
I can see with the original code was that I forgot that this runs after type legalization and hence the result type will always be i32. (Custom legalization of EXTRACT_VECTOR_ELT is only enabled for vector types with 8- and 16-bit elements.) Regarding the FIXME comment: any information about sign and zero-extension should be captured by separate extension operations. The DAG combiner should handle those to produce either VGETLANEu or VGETLANEs, and that seems to be working now. If there are cases that we're missing, let me know. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84218 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2026-02-15 08:02:47 +0000