aboutsummaryrefslogtreecommitdiff
path: root/lib/Target/ARM/ARMISelLowering.cpp
AgeCommit message (Collapse)Author
2011-06-10Provide an ARMCCState subclass of CCState so that ARM clients will always setCameron Zwarich
CallOrPrologue correctly and eliminate the existing setter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132856 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09A CCState was being created without setting whether it is in the Call or ↵Cameron Zwarich
Prologue state, causing an assertion failure downstream. This fixes <rdar://problem/9562908>. This really seems like it should always be set at CCState creation time, so mistakes like this can never happen. I'll take a look at doing that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-08Add a parameter to CCState so that it can access the MachineFunction.Eric Christopher
No functional change. Part of PR6965 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132763 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03Make the Uv constraint a memory operand. This doesn't solve theEric Christopher
addressing mode problem mentioned in r132559. Backend part of rdar://9037836 and part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132561 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Have LowerOperandForConstraint handle multiple character constraints.Eric Christopher
Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132510 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.John McCall
This is important for the correct lowering of unwind instructions (which doesn't matter at all) and llvm.eh.resume calls (which does). Take 2, now with more basic competence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132295 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29I didn't mean to commit these residues of a personal project.John McCall
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132293 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.John McCall
This is important for the correct lowering of unwind instructions (which doesn't matter at all) and llvm.eh.resume calls (which does). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132291 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairsBruno Cardoso Lopes
to load/store i64 values. Since there's no current support to explicitly declare such restrictions, implement it by using specific hardcoded register pairs during isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132248 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27Fix the remaining atomic intrinsics to use the right register classes on Thumb2,Cameron Zwarich
and add some basic tests for them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132235 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27Don't use movw / movt for iOS static codegen for now to workaround some ↵Evan Cheng
tools issues. rdar://9514789 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132211 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-22RTABI chapter 4.3.4 specifies __eabi_mem* calls. Specifically, __eabi_memset ↵Renato Golin
accepts parameters (ptr, size, value) in a different order than GNU's memset (ptr, value, size), therefore the special lowering in AAPCS mode. Implementation by Evzen Muller. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131868 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20Revert accidental commit.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131739 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20Revert r131664 and fix it in instcombine instead. rdar://9467055Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131708 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19Fixed sdiv and udiv for <4 x i16>. The test from r125402 still applies for ↵Mon P Wang
this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131630 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18Handle perfect shuffle case that generates a vrev for vectors of floats.Tanya Lattner
Add test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131582 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18Revise r131553. Just use the type of the input node and forgo the bitcast. ↵Evan Cheng
rdar://9449159. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131555 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18Fix an ARMTargetLowering::LowerSELECT bug: legalized result must have same ↵Evan Cheng
type as input. Sorry test cases only trigger when dag combine is disabled. rdar://9449178 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131553 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18In r131488 I misunderstood how VREV works. It splits the vector in half and ↵Tanya Lattner
splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32. Updated test case and reverted change to the PerfectShuffle Table. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131529 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18Fix typo.Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131519 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18Fix more of PR8825 by correctly using rGPR registers when lowering atomicCameron Zwarich
compare-and-swap intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-11Give the 'eh.sjlj.dispatchsetup' intrinsic call the value coming from the setjmpBill Wendling
intrinsic call. This prevents it from being reordered so that it appears *before* the setjmp intrinsic (thus making it completely useless). <rdar://problem/9409683> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131174 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-06Make the logic for determining function alignment more explicit. No ↵Eli Friedman
functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131012 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03Temporarily disable use of divmod compiler-rt functions for iOS.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130766 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03Add an unfolded offset field to LSR's Formula record. This is used toDan Gohman
model constants which can be added to base registers via add-immediate instructions which don't require an additional register to materialize the immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130743 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-2980-col.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130558 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-26ARM and Thumb2 support for atomic MIN/MAX/UMIN/UMAX loads.Jim Grosbach
rdar://9326019 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130234 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-23Thumb2 and ARM add/subtract with carry fixes.Andrew Trick
Fixes Thumb2 ADCS and SBCS lowering: <rdar://problem/9275821>. t2ADCS/t2SBCS are now pseudo instructions, consistent with ARM, so the assembly printer correctly prints the 's' suffix. Fixes Thumb2 adde -> SBC matching to check for live/dead carry flags. Fixes the internal ARM machine opcode mnemonic for ADCS/SBCS. Fixes ARM SBC lowering to check for live carry (potential bug). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130048 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Remove -use-divmod-libcall. Let targets opt in when they are available.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Excise unintended hunk in 129858. <rdar://problem/7662569>Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129862 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20ARM byval support. Will be enabled by another patch to the FE. ↵Stuart Hastings
<rdar://problem/7662569> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129858 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19Remove some duplicate op action entries and reorganize.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129781 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15Fix a ton of comment typos found by codespell. Patch byChris Lattner
Luis Felipe Strano Moraes! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15Fix another fcopysign lowering bug. If src is f64 and destination is f32, don'tEvan Cheng
forget to right shift the source by 32 first. rdar://9287902 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129556 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13Fix a typo in an ARM-specific DAG combine. This fixes <rdar://problem/9278274>.Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129468 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARMCameron Zwarich
stores of arguments in the same cache line. This fixes the second half of <rdar://problem/8674845>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129345 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-08Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap ↵Evan Cheng
is lowered into a call to the specified trap function at sdisel time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129152 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07Add option to emit @llvm.trap as a function call instead of a trap ↵Evan Cheng
instruction. rdar://9249183. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129107 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal ↵Tanya Lattner
vector type (vectors of size 3). Also included test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129074 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07Change -arm-divmod-libcall to a target neutral option.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129045 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Reapply r128946 (pseudoization of various instructions), and fix the extra ↵Owen Anderson
imp-def of CPSR it was adding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128965 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Revert r128946 while I figure out why it broke the buildbots.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Give RSBS and RSCS the pseudo treatment.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128946 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as ↵Owen Anderson
doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128940 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Revamp the SjLj "dispatch setup" intrinsic.Bill Wendling
It needed to be moved closer to the setjmp statement, because the code directly after the setjmp needs to know about values that are on the stack. Also, the 'bitcast' of the function context was causing a dead load. This wouldn't be too horrible, except that at -O0 it wasn't optimized out, and because it wasn't using the correct base pointer (if there is a VLA), it would try to access a value from a garbage address. <rdar://problem/9130540> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128873 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02Do some peephole optimizations to remove pointless VMOVs from Neon to integerCameron Zwarich
registers that arise from argument shuffling with the soft float ABI. These instructions are particularly slow on Cortex A8. This fixes one half of <rdar://problem/8674845>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128759 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs.Evan Cheng
rdar://8911343 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplierEvan Cheng
accumulator forwarding: vadd d3, d0, d1 vmul d3, d3, d2 => vmul d3, d0, d2 vmla d3, d1, d2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128665 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-30Don't try to create zero-sized stack objects.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128586 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-30Add a ARM-specific SD node for VBSL so that forms with a constant first operandCameron Zwarich
can be recognized. This fixes <rdar://problem/9183078>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128584 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2026-02-11 21:08:11 +0000