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path: root/lib/Target/ARM/ARMISelLowering.cpp
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2010-11-10Fix an issue where we tried to turn a v2f32 build_vector into a v4i32 build ↵Nate Begeman
vector with 2 elts git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118720 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Do not use MEMBARRIER_MCR for any Thumb code.Bob Wilson
It is only supported for ARM code. Normally Thumb2 code would use DMB instead, but depending on how the compiler is invoked (e.g., -mattr=-db) that might be disabled. This prevents a "cannot select MEMBARRIER_MCR" error in that situation. Radar 8644195 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118642 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Change the ARMConstantPoolValue modifier string to an enumeration. This willJim Grosbach
help in MC'izing the references that use them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118633 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08Add support for ARM's specialized vector-compare-against-zero instructions.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05Disallow the certain NEON modified-immediate forms when generating vorr or vbic.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118300 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05Add codegen and encoding support for the immediate form of vbic.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118291 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04Fix @llvm.prefetch isel. Selecting between pld / pldw using the first ↵Evan Cheng
immediate rw. There is currently no intrinsic that matches to pli. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118237 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03Covert VORRIMM to be produced via early target-specific DAG combining, ↵Owen Anderson
rather than legalization. This is both the conceptually correct place for it, as well as allowing it to be more aggressive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03Add support for code generation of the one register with immediate form of vorr.Owen Anderson
We could be more aggressive about making this work for a larger range of constants, but this seems like a good start. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03Check for extractelement with a variable operand for the element number.Bob Wilson
For NEON we had been assuming this was always an immediate constant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118175 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03Simplify uses of MVT and EVT. An MVT can be compared directlyDuncan Sands
with a SimpleValueType, while an EVT supports equality and inequality comparisons with SimpleValueType. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118169 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03Fix preload instruction isel. Only v7 supports pli, and only v7 with mp ↵Evan Cheng
extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118160 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118152 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01NEON does not support truncating vector stores. Radar 8598391.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117940 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30Overhaul memory barriers in the ARM backend. Radar 8601999.Bob Wilson
There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117756 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29- Don't schedule nodes with only MVT::Flag and MVT::Other values for latency.Evan Cheng
- Compute CopyToReg use operand latency correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117674 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29Inline asm multiple alternative constraints development phase 2 - improved ↵John Thompson
basic logic, added initial platform support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117667 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Fix compiler warnings about signed/unsigned comparisons.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117511 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27SelectionDAG shuffle nodes do not allow operands with different numbers ofBob Wilson
elements than the result vector type. So, when an instruction like: %8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2> is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is: shuffle [a,b], [c,d] is changed to: shuffle [a,b,u,u], [c,d,u,u] That's probably the right thing for x86 but for NEON, we'd much rather have: shuffle [a,b,c,d], undef Teach the DAG combiner how to do that transformation for ARM. Radar 8597007. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117482 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-23Enable ARM fastcc.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22Add fastcc cc: pass and return VFP / NEON values in registers. Controlled by ↵Evan Cheng
-arm-fastcc for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117119 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20Fix crash introduced in 116852. 8573915.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do anyJim Grosbach
setup they require. Use this for ARM/Darwin to rematerialize the base pointer from the frame pointer when required. rdar://8564268 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19Enable using vdup for vector constants which are splat ofDale Johannesen
integers by default, and remove the controlling flag, now that LICM will hoist such vdup's. 8003375. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116852 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15Don't mark argument value stores as immutable, as otherwise the post-RAJim Grosbach
scheduler may reorder loads from them before the stores and other such badness. PR8347. Patch by David Meyer git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116602 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15Remove unused ARMISD::AND selection DAG node.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116566 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28User proper libcall names & condcodes while compiling for ARM EABI.Anton Korobeynikov
Patch by Evzen Muller! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28Add a command line option "-arm-strict-align" to disallow unaligned memoryBob Wilson
accesses for ARM targets that would otherwise allow it. Radar 8465431. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-24Enable code placement optimization pass for ARM.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22Add support for ELF PLT references for ARM MC asm printing. Adding aJim Grosbach
new VariantKind to the MCSymbolExpr seems like overkill, but I'm not sure there's a more straightforward way to get the printing difference captured. (i.e., x86 uses @PLT, ARM uses (PLT)). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114613 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22Change VDUPLANE DAG combiner to just return the result instead of callingBob Wilson
CombineTo to avoid putting the result on the worklist. I don't think it makes much difference for now, but it might help someday as we add more DAG combine optimizations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114595 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22Combine both VMOVDRR(VMOVRRD) and VMOVRRD(VMOVDRR), instead of just doing oneBob Wilson
of those. Refactor to share code for handling BUILD_VECTOR(VMOVRRD). I don't have a testcase that exercises this, but it seems like an obvious good thing to do. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114589 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that ↵Owen Anderson
this makes irrelevant, but add a new test for the new, improved functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114494 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21convert a couple more places to use the new getStore()Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114463 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21Define the TargetLowering::getTgtMemIntrinsic hook for ARM so that NEON loadBob Wilson
and store intrinsics are represented with MemIntrinsicSDNodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114454 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21convert the targets off the non-MachinePointerInfo of getLoad.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114410 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21reimplement memcpy/memmove/memset lowering to use MachinePointerInfoChris Lattner
instead of srcvalue/offset pairs. This corrects SV info for mem operations whose size is > 32-bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114401 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64Bob Wilson
value should be in GPRs when it's going to be used as a scalar, and we use VMOVRRD to make that happen, but if the value is converted back to a vector we need to fold to a simple bit_convert. Radar 8407927. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10Split out some of the calling convention bits so that they can beEric Christopher
used for fast-isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113652 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10Teach if-converter to be more careful with predicating instructions that wouldEvan Cheng
take multiple cycles to decode. For the current if-converter clients (actually only ARM), the instructions that are predicated on false are not nops. They would still take machine cycles to decode. Micro-coded instructions such as LDM / STM can potentially take multiple cycles to decode. If-converter should take treat them as non-micro-coded simple instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08remove trailing whitespaceJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113338 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03Replace NEON vabdl, vaba, and vabal intrinsics with combinations of theBob Wilson
vabd intrinsic and add and/or zext operations. In the case of vaba, this also avoids the need for a DAG combine pattern to combine vabd with add. Update tests. Auto-upgrade the old intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with multiply,Bob Wilson
add, and subtract operations with zero-extended or sign-extended vectors. Update tests. Add auto-upgrade support for the old intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112773 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29Create an ARMISD::AND node. This node is exactly like the "ARM::AND" node, butBill Wendling
it sets the CPSR register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112393 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25ARM/Thumb2: Fix a misselect in getARMCmp, when attempting to adjust a signedDaniel Dunbar
comparison that would overflow. - The other under/overflow cases can't actually happen because the immediates which would trigger them are legal (so we don't enter this code), but adjusted the style to make it clear the transform is always valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112053 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-20Replace the arm.neon.vmovls and vmovlu intrinsics with vector sign-extend andBob Wilson
zero-extend operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111614 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18Expand ZERO_EXTEND operations for NEON vector types.Bob Wilson
Testcase from Nick Lewycky. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111341 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17Allow more cases of undef shuffle indices and add tests for them.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111226 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-16Ignore undef shuffle indices when checking for a VTRN shuffle. Radar 8290937.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111208 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13Temporarily disable tail calls on ARM to work around some linker problems.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111050 91177308-0d34-0410-b5e6-96231b3b80d8
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