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Age	Commit message (Expand)	Author
2012-09-13	This patch introduces A15 as a target in LLVM.	Silviu Baranga
2012-09-04	Patch to implement UMLAL/SMLAL instructions for the ARM architecture	Arnold Schwaighofer
2012-08-18	Remove the CAND/COR/CXOR custom ISD nodes and their select code.	Jakob Stoklund Olesen
2012-08-15	Add missing Rfalse operand to the predicated pseudo-instructions.	Jakob Stoklund Olesen
2012-08-12	Revert 161581: Patch to implement UMLAL/SMLAL instructions for the ARM	Arnold Schwaighofer
2012-08-09	Patch to implement UMLAL/SMLAL instructions for the ARM architecture	Arnold Schwaighofer
2012-08-01	Clean up formatting.	Jim Grosbach
2012-08-01	Tidy up.	Jim Grosbach
2012-05-24	Make some opcode tables static and const. Allows code to avoid making copies ...	Craig Topper
2012-04-26	Test commit.	Tim Northover
2012-04-11	ARM 'vuzp.32 Dd, Dm' is a pseudo-instruction.	Jim Grosbach
2012-04-11	ARM 'vzip.32 Dd, Dm' is a pseudo-instruction.	Jim Grosbach
2012-03-06	ARM refactor more NEON VLD/VST instructions to use composite physregs	Jim Grosbach
2012-03-05	ARM refactor away a bunch of VLD/VST pseudo instructions.	Jim Grosbach
2012-02-23	Remove unused variable.	Duncan Sands
2012-02-23	Optimize a couple of common patterns involving conditional moves where the false	Evan Cheng
2012-02-07	Convert assert(0) to llvm_unreachable	Craig Topper
2012-01-20	More dead code removal (using -Wunreachable-code)	David Blaikie
2012-01-10	ARM updating VST2 pseudo-lowering fixed vs. register update.	Jim Grosbach
2011-12-21	ARM NEON assmebly parsing for VLD2 to all lanes instructions.	Jim Grosbach
2011-12-14	ARM NEON refactor VST2 w/ writeback instructions.	Jim Grosbach
2011-12-09	ARM assembly parsing and encoding for VLD2 with writeback.	Jim Grosbach
2011-11-29	ARM assembly parsing and encoding for four-register VST1.	Jim Grosbach
2011-11-29	ARM assembly parsing and encoding for three-register VST1.	Jim Grosbach
2011-10-31	ARM VST1 w/ writeback assembly parsing and encoding.	Jim Grosbach
2011-10-27	Also set addrmode6 alignment when align==size.	Jakob Stoklund Olesen
2011-10-27	ARM isel for vld1, opcode selection for register stride post-index pseudos.	Jim Grosbach
2011-10-24	ARM refactor am6offset usage for VLD1.	Jim Grosbach
2011-10-18	Fix misc warnings. Patch by Joe Abbey.	Eli Friedman
2011-10-10	Reapply r141365 now that PR11107 is fixed.	Bill Wendling
2011-10-10	Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to	Bill Wendling
2011-10-08	Disable ABS optimization for Thumb1 target, we don't have necessary instructi...	Anton Korobeynikov
2011-10-07	Peephole optimization for ABS on ARM.	Anton Korobeynikov
2011-10-05	Always merge profitable shifts on A9, not just when they have a single use.	Cameron Zwarich
2011-10-05	Remove a check from ARM shifted operand isel helper methods, which were blocking	Cameron Zwarich
2011-10-05	Add braces around something that throws me for a loop.	Cameron Zwarich
2011-10-05	There is no point in setting out-parameters for a ComplexPattern function when	Cameron Zwarich
2011-09-23	Also match negative offsets for addrmode3 and addrmode5.	Jakob Stoklund Olesen
2011-09-13	Tidy up a few 80 column violations.	Jim Grosbach
2011-08-31	When performing instruction selection for LDR_PRE_IMM/LDRB_PRE_IMM, we still ...	Owen Anderson
2011-08-31	64-bit atomic cmpxchg for ARM.	Eli Friedman
2011-08-31	Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.	Eli Friedman
2011-08-29	addrmode_imm12 and addrmode2_offset encode their immediate values differently...	Owen Anderson
2011-08-26	Fix ARM codegen breakage caused by r138653.	Owen Anderson
2011-08-26	invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We w...	Owen Anderson
2011-08-24	Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.	Jim Grosbach
2011-08-05	ARM refactor indexed store instructions.	Jim Grosbach
2011-07-27	ARM parsing and encoding of SBFX and UBFX.	Jim Grosbach
2011-07-26	Split am2offset into register addend and immediate addend forms, necessary fo...	Owen Anderson
2011-07-22	Fix test failures caused by my so_reg refactoring.	Owen Anderson