| Age | Commit message (Expand) | Author |
|---|
| 2009-05-19 | Fix pr4091: Add support for "m" constraint in ARM inline assembly. | Bob Wilson |
| 2009-04-07 | PR2985 / <rdar://problem/6584986> | Jim Grosbach |
| 2009-03-26 | tADDhirr is a thumb instruction. Do not allow this code to be reached in non-... | Evan Cheng |
| 2009-02-12 | fix PR3538 for ARM. | Chris Lattner |
| 2009-02-06 | Eliminate remaining non-DebugLoc version of getTargetNode. | Dale Johannesen |
| 2009-02-06 | get rid of some non-DebugLoc getTargetNode variants. | Dale Johannesen |
| 2009-02-06 | Get rid of one more non-DebugLoc getNode and | Dale Johannesen |
| 2009-01-15 | Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph | Dan Gohman |
| 2008-12-10 | Preliminary ARM debug support based on patch by Mikael of FlexyCore. | Evan Cheng |
| 2008-12-03 | Update a comment. | Dan Gohman |
| 2008-11-05 | Eliminate the ISel priority queue, which used the topological order for a | Dan Gohman |
| 2008-10-27 | Have TableGen emit setSubgraphColor calls under control of a -gen-debug | David Greene |
| 2008-10-03 | Avoid creating two TargetLowering objects for each target. | Dan Gohman |
| 2008-09-18 | Cosmetic. | Evan Cheng |
| 2008-09-12 | Rename ConstantSDNode::getValue to getZExtValue, for consistency | Dan Gohman |
| 2008-08-28 | erect abstraction boundaries for accessing SDValue members, rename Val -> Nod... | Gabor Greif |
| 2008-08-26 | disallow direct access to SDValue::ResNo, provide a getter instead | Gabor Greif |
| 2008-08-23 | Move the point at which FastISel taps into the SelectionDAGISel | Dan Gohman |
| 2008-08-21 | Simplify SelectRoot's interface, and factor out some common code | Dan Gohman |
| 2008-07-27 | Rename SDOperand to SDValue. | Dan Gohman |
| 2008-07-17 | Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk | Dan Gohman |
| 2008-07-07 | Add explicit keywords. | Dan Gohman |
| 2008-06-30 | Split scheduling from instruction selection. | Evan Cheng |
| 2008-06-06 | Wrap MVT::ValueType in a struct to get type safety | Duncan Sands |
| 2008-02-04 | Dwarf requires variable entries to be in the source order. Right now, since w... | Evan Cheng |
| 2008-02-03 | explicitly include Compiler.h instead of getting it from tblgen in the middle... | Chris Lattner |
| 2008-02-03 | don't do ReplaceUses on a result that doesn't exist. | Chris Lattner |
| 2008-02-02 | SDIsel processes llvm.dbg.declare by recording the variable debug information... | Evan Cheng |
| 2008-01-30 | Factor the addressing mode and the load/store VT out of LoadSDNode | Dan Gohman |
| 2007-12-31 | Rename SSARegMap -> MachineRegisterInfo in keeping with the idea | Chris Lattner |
| 2007-12-29 | Remove attribution from file headers, per discussion on llvmdev. | Chris Lattner |
| 2007-10-08 | Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to | Dan Gohman |
| 2007-07-10 | Remove clobbersPred. Add an OptionalDefOperand to instructions which have the... | Evan Cheng |
| 2007-07-05 | Unfortunately we now require C++ code to isel Bcc, conditional moves, etc. | Evan Cheng |
| 2007-05-15 | Add PredicateOperand to all ARM instructions that have the condition field. | Evan Cheng |
| 2007-05-03 | match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll | Chris Lattner |
| 2007-03-19 | Fix naming inconsistencies. | Evan Cheng |
| 2007-03-19 | Special LDR instructions to load from non-pc-relative constantpools. These are | Evan Cheng |
| 2007-03-13 | AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2] | Evan Cheng |
| 2007-02-07 | Get rid of references to iostream. | Evan Cheng |
| 2007-02-06 | Select add FI, c correctly. | Evan Cheng |
| 2007-02-06 | - Store val, [sp, c] must be selected to tSTRsp. | Evan Cheng |
| 2007-01-30 | Change the operand orders to t_addrmode_s* to make it easier to morph | Evan Cheng |
| 2007-01-24 | Use PC relative ldr to load from a constantpool in Thumb mode. | Evan Cheng |
| 2007-01-24 | Allow [ fi#c, imm ] as ARM load / store addresses. | Evan Cheng |
| 2007-01-24 | Various Thumb mode load / store isel bug fixes. | Evan Cheng |
| 2007-01-23 | - Reorg Thumb load / store instructions. Combine each rr and ri pair of | Evan Cheng |
| 2007-01-19 | ARM backend contribution from Apple. | Evan Cheng |
| 2007-01-12 | Build constants using instructions mov/orr or mvn/eor. | Lauro Ramos Venancio |
| 2007-01-04 | Expand SELECT (f32/f64) and FCOPYSIGN (f32/f64). | Lauro Ramos Venancio |
