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path: root/lib/Target/ARM/ARMFastISel.cpp
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2011-12-04Fix 80-column issues.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145783 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-03[arm-fast-isel] Unaligned stores of floats require special care.Chad Rosier
rdar://10510150 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145742 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky
change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02[arm-fast-isel] After promoting a function parameter be sure to update theChad Rosier
argument value type. Otherwise, the sign/zero-extend has no effect on arguments passed via the stack (i.e., undefined high-order bits). rdar://10515467 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145701 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-28Silence wrong warnings from GCC about variables possibly being usedDuncan Sands
uninitialized: GCC doesn't understand that the variables are only used if !UseImm, in which case they have been initialized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145239 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-18Guard call to getRegForValue with isTypeLegal check to avoid unnecessary ↵Chad Rosier
work/dead code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144959 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17Add TODO comment.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144920 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17Dead code.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144888 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17Don't unconditionally set the kill flag.Chad Rosier
rdar://10456186 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144872 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16Check to make sure we can select the instruction before trying to put theChad Rosier
operands into a register. Otherwise, we may materialize dead code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144805 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16Add FIXME comment.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144743 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15Remove some unnecessary includes of PseudoSourceValue.h.Jay Foad
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144631 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14Supporting inline memmove isn't going to be worthwhile. The only way to avoidChad Rosier
violating a dependency is to emit all loads prior to stores. This would likely cause a great deal of spillage offsetting any potential gains. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144585 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14Add support for inlining small memcpys.Chad Rosier
rdar://10412592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144578 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14Fix a performance regression from r144565. Positive offsets were being loweredChad Rosier
into registers, rather then encoded directly in the load/store. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144576 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14Add support for Thumb load/stores with negative offsets.Chad Rosier
rdar://10412592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144565 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14Add support for ARM halfword load/stores and signed byte loads with negativeChad Rosier
offsets. rdar://10412592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13The order in which the predicate is added differs between Thumb and ARM ↵Chad Rosier
mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144494 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing ↵Chad Rosier
failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144492 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13Fix comments.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144490 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13Add support for emitting both signed- and zero-extend loads. Fix Chad Rosier
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8 offsets (addressing mode 3). This enables a load followed by an integer extend to be folded into a single load. For example: ldrb r1, [r0] ldrb r1, [r0] uxtb r2, r1 => mov r3, r2 mov r3, r1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144426 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11Rename variables to avoid confusion. No functionallity change intended.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144377 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11Add support for using immediates with select instructions.Chad Rosier
rdar://10412592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144376 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11When loading a value, treat an i1 as an i8.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144356 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11Add support for using MVN to materialize negative constants.Chad Rosier
rdar://10412592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144348 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10When in ARM mode, LDRH/STRH require special handling of negative offsets.Chad Rosier
For correctness, disable this for now. rdar://10418009 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144316 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10For immediate encodings of icmp, zero or sign extend first. ThenChad Rosier
determine if the value is negative and flip the sign accordingly. rdar://10422026 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144258 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-09The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12.Chad Rosier
rdar://10418009 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144213 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-09Add support for encoding immediates in icmp and fcmp. Hopefully, this willChad Rosier
remove a fair number of unnecessary materialized constants. rdar://10412592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144163 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-08ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this.Chad Rosier
No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144122 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-08Enable support for returning i1, i8, and i16. Nothing special todo as it's theChad Rosier
callee's responsibility to sign or zero-extend the return value. The additional test case just checks to make sure the calls are selected (i.e., -fast-isel-abort doesn't assert). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144047 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-05Add support for passing i1, i8, and i16 call parameters. Also, be sure toChad Rosier
zero-extend the constant integer encoding. Test case provides testing for both call parameters and materialization of i1, i8, and i16 types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143821 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-04Cannot create a result register for non-legal types.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143749 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-04When materializing an i32, SExt vs ZExt doesn't matter when we're trying to fitChad Rosier
in a 16-bit immediate. However, for the shorter non-legal types (i.e., i1, i8, i16) we should not sign-extend. This prevents us from materializing things such as 'true' (i.e., i1 1). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143743 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-04Enable support for materializing i1, i8, and i16 integers via move immediate.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143739 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-04Indentation.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143670 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-04Add fast-isel support for returning i1, i8, and i16.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143669 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-03Add support for sign-extending non-legal types in SelectSIToFP().Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143603 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-02Add support for comparing integer non-legal types.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143559 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-02Factor out an EmitIntExt function. No functionality change intended.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143547 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-02Factor out a SelectTrunc function. No functionality change intended.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143523 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-27A branch predicated on a constant can just FastEmit an unconditional branch.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143086 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26Add a TODO comment. FastISel works by parsing each basic block from the bottomChad Rosier
up. Thus, improving the support for compares is goodness because it increases the number of terminator instructions we can handle. This creates many more opportunities for target specific fast-isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143079 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26Factor a little more code into EmitCmp, which should have been done in the firstChad Rosier
place. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143078 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26Use EmitCmp in SelectBranch. No functional change intended.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143076 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26Factor out an EmitCmp function that can be used by both SelectCmp andChad Rosier
SelectBranch. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143072 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Add a few FIXME comments.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142299 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01Switch over to using ARMConstantPoolConstant for global variables, functions,Bill Wendling
and block addresses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.Jim Grosbach
Encode the immediate into its 8-bit form as part of isel rather than later, which simplifies things for mapping the encoding bits, allows the removal of the custom disassembler decoding hook, makes the operand printer trivial, and prepares things more cleanly for handling these in the asm parser. rdar://10211428 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140834 91177308-0d34-0410-b5e6-96231b3b80d8
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