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registers that should be renamed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85939 91177308-0d34-0410-b5e6-96231b3b80d8
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information to avoid chaining loads/stores of spill slots with non-aliased memory ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85934 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85909 91177308-0d34-0410-b5e6-96231b3b80d8
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warning from gcc by removing VISIBILITY_HIDDEN attributes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85873 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85827 91177308-0d34-0410-b5e6-96231b3b80d8
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(except for true dependency of Store followed by aliased Load... we estimate that case with a single cycle of latency assuming the hardware will bypass)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85807 91177308-0d34-0410-b5e6-96231b3b80d8
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hoisted to
the loop preheader. Add instructions which are already in the preheader block that
may be common expressions of those that are hoisted out. These does get a few more
instructions CSE'ed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85799 91177308-0d34-0410-b5e6-96231b3b80d8
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alias any LLVM IR value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85762 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85684 91177308-0d34-0410-b5e6-96231b3b80d8
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- Be consistent when referring to MachineBasicBlocks: BB#0.
- Be consistent when referring to virtual registers: %reg1024.
- Be consistent when referring to unknown physical registers: %physreg10.
- Be consistent when referring to known physical registers: %RAX
- Be consistent when referring to register 0: %reg0
- Be consistent when printing alignments: align=16
- Print jump table contents.
- Don't print host addresses, in general.
- and various other cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85682 91177308-0d34-0410-b5e6-96231b3b80d8
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previously running CodePlacementOpt. Also print headers before
each dump in -print-machineinstrs mode, so that it's clear which
dump is which.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85681 91177308-0d34-0410-b5e6-96231b3b80d8
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to unfold loop-invariant loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85657 91177308-0d34-0410-b5e6-96231b3b80d8
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that uses this information knows to behave conservatively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85654 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85653 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85648 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85639 91177308-0d34-0410-b5e6-96231b3b80d8
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results. This works around a problem affecting targets which rely on
MVT::Flag to handle physical register defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85638 91177308-0d34-0410-b5e6-96231b3b80d8
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unfolding loads for hoisting. getOpcodeAfterMemoryUnfold returns the
opcode of the original operation without the load, not the load
itself, MachineLICM needs to know the operand index in order to get
the correct register class. Extend getOpcodeAfterMemoryUnfold to
return this information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85622 91177308-0d34-0410-b5e6-96231b3b80d8
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interval.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85599 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85562 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85559 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85558 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85556 91177308-0d34-0410-b5e6-96231b3b80d8
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that we don't incorrectly rename registers that span these regions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85537 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85536 91177308-0d34-0410-b5e6-96231b3b80d8
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*ISelDAGToDAG.cpp to being regular code in SelectionDAGISel.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85530 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85522 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85519 91177308-0d34-0410-b5e6-96231b3b80d8
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bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85515 91177308-0d34-0410-b5e6-96231b3b80d8
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indexed via the stack pointer, even if a frame pointer is present. Update the
heuristic to place it nearest the stack pointer in that case, rather than
nearest the frame pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85474 91177308-0d34-0410-b5e6-96231b3b80d8
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the second (store) instruction in SpillSlotToUsesMap
consistently. I don't think this matters functionally,
but it's cleaner and Evan wants it this way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85463 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85460 91177308-0d34-0410-b5e6-96231b3b80d8
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--- Reverse-merging r85338 into '.':
U lib/CodeGen/SimpleRegisterCoalescing.cpp
U lib/CodeGen/SimpleRegisterCoalescing.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85454 91177308-0d34-0410-b5e6-96231b3b80d8
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common tail, except when the OptimizeForSize function attribute is present.
Radar 7338114.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85441 91177308-0d34-0410-b5e6-96231b3b80d8
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to spill after all, we weren't handling 2-instruction
spill sequences correctly (PPC Altivec). We need to
remove the store in this case. Removing the other
instruction(s) would be goodness but is not needed for
correctness, and isn't done here. 7331562.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85437 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85436 91177308-0d34-0410-b5e6-96231b3b80d8
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I'm going to redo this using the OptimizeForSize function attribute.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85426 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85412 91177308-0d34-0410-b5e6-96231b3b80d8
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chains have no users, they can't be predecessors of the condition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85394 91177308-0d34-0410-b5e6-96231b3b80d8
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the new instructions and leave the old one in place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85393 91177308-0d34-0410-b5e6-96231b3b80d8
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recursive to avoid consuming extraordinary amounts of stack space
when processing tall graphs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85369 91177308-0d34-0410-b5e6-96231b3b80d8
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otherwise unhoistable instructions in order to allow the loads
to be hoisted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85364 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85361 91177308-0d34-0410-b5e6-96231b3b80d8
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MachineLICM and other things which run before LiveVariables is run.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85360 91177308-0d34-0410-b5e6-96231b3b80d8
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if they have compatible encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85359 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85351 91177308-0d34-0410-b5e6-96231b3b80d8
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