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the variable actually tracks.
N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.
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optimizer.
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- Kill is implicit when use and def registers are identical.
- Only virtual registers can differ.
Add a -verify-fast-regalloc to run the verifier before the fast allocator.
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This adds extra security against using clobbered physregs, and it adds kill
markers to physreg uses.
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-filetype=obj test, and -filetype=obj leaks a few objects. Added a FIXME, we
need to sort out the ownership model for the various MC objects.
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printed.
- This is a hack, but I can't decide the best place to handle this. Chris?
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This loop is quadratic in the capacity for a DenseMap:
while(!map.empty())
map.erase(map.begin());
Instead we now do a normal begin() - end() iteration followed by map.clear().
That also has the nice sideeffect of shrinking the map capacity on demand.
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one was subject to double rounding in extreme cases.
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when they move instructions.
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use of it in MachineCSE.
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basic block.
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This causes way more identity copies to be generated, ripe for coalescing.
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information when a copy is introduced.
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do not match.
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The X86 floating point stack pass and others depend on good kill flags.
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Now, the .linkonce directive is emitted as part of MCSectionCOFF::PrintSwitchToSection instead of AsmPrinter::EmitLinkage since it is an attribute of the section the symbol was placed into not the symbol itself.
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This allows us to add accurate kill markers, something the scavenger likes.
Add some more tests from ARM that needed this.
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create separate virtual registers for CopyFromReg values, so uses of
them don't necessarily kill the value.
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closure after allocating all blocks.
Add a few more test cases for -regalloc=fast.
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to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is
the opposite, for future use by dragonegg.
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Sorry for the big change. The path leading up to this patch had some TableGen
changes that I didn't want to commit before I knew they were useful. They
weren't, and this version does not need them.
The fast register allocator now does no liveness calculations. Instead it relies
on kill flags provided by isel. (Currently those kill flags are also ignored due
to isel bugs). The allocation algorithm is supposed to work with any subset of
valid kill flags. More kill flags simply means fewer spills inserted.
Registers are allocated from a working set that contains no aliases. That means
most allocations can be done directly without expensive alias checks. When the
working set runs out of registers we do the full alias check to find new free
registers.
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Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.
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indices.
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This means now 'llvm-ld a.bc b.bc' will preserve debug info appropriately.
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operands may be the same. PR7018. rdar://7939869.
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SSAUpdater for the value from the first def may see uses of undefined values,
because the later defs will not have been updated yet.
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Based on a patch by Javier Martinez.
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namespace etc..
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and not the real problem itself, by dropping debug info for i128 values.
rdar://7958162.
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