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2010-06-15IfConversion's AnalyzeBlocks method always returns false; clean it up.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106027 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15fix namingJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106024 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15Fix an exotic bug that only showed up in an internal test case.Jakob Stoklund Olesen
SimpleRegisterCoalescing::JoinIntervals() uses CoalescerPair to determine if a copy is coalescable, and in very rare cases it can return true where LHS is not live - the coalescable copy can come from an alias of the physreg in LHS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15Fix a comment typo.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106015 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15Add some missing checks for the case where the extract_subregs areBob Wilson
combined to an insert_subreg, i.e., where the destination register is larger than the source. We need to check that the subregs can be composed for that case in a symmetrical way to the case when the destination is smaller. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106004 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15Avoid processing early clobbers twice in RegAllocFast.Jakob Stoklund Olesen
Early clobbers defining a virtual register were first alocated to a physreg and then processed as a physreg EC, spilling the virtreg. This fixes PR7382. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105998 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15Add CoalescerPair helper class.Jakob Stoklund Olesen
Given a copy instruction, CoalescerPair can determine which registers to coalesce in order to eliminate the copy. It deals with all the subreg fun to determine a tuple (DstReg, SrcReg, SubIdx) such that: - SrcReg is a virtual register that will disappear after coalescing. - DstReg is a virtual or physical register whose live range will be extended. - SubIdx is 0 when DstReg is a physical register. - SrcReg can be joined with DstReg:SubIdx. CoalescerPair::isCoalescable() determines if another copy instruction is compatible with the same tuple. This fixes some NEON miscompilations where shuffles are getting coalesced as if they were copies. The CoalescerPair class will replace a lot of the spaghetti logic in JoinCopy later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105997 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15Generalize the pre-coalescing of extract_subregs feeding reg_sequences,Bob Wilson
replacing the overly conservative checks that I had introduced recently to deal with correctness issues. This makes a pretty noticable difference in our testcases where reg_sequences are used. I've updated one test to check that we no longer emit the unnecessary subreg moves. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15Update CMake build.Ted Kremenek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-14More dbg_value cleanup so the presence of debug info doesn't affect code-gen.Jim Grosbach
Make sure to skip the dbg_value instructions when moving dups out of the diamond. rdar://7797940 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105965 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-14- Do away with SimpleHazardRecognizer.h. It's not used and offers little value.Evan Cheng
- Rename ExactHazardRecognizer to PostRAHazardRecognizer and move its header to include to allow targets to extend it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105959 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-14Avoid uncessary array copying.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-14fix a -Wbool-conversions warning from clang.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105942 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-12When performing the Horrible Hack(tm-Duncan) on the EH code to convert aBill Wendling
clean-up to a catch-all after inlining, take into account that there could be filter IDs as well. The presence of filters don't mean that the selector catches anything. It's just metadata information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105872 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-12Allow target to provide its own hazard recognizer to post-ra scheduler.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105862 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-12Code formatting.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105861 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-11Support for nested functions/classes in debug output. (Again.) Radar 7424645.Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105828 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-10Code refactoring, no functionality changes.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105775 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09Mark physregs defined by inline asm as implicit.Jakob Stoklund Olesen
This is a bit of a hack to make inline asm look more like call instructions. It would be better to produce correct dead flags during isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105749 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09Allow target to place 2-address pass inserted copies in better spots. Thumb2 ↵Evan Cheng
will use this to try to avoid breaking up IT blocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09It's an error to translate this:Bill Wendling
%reg1025 = <sext> %reg1024 ... %reg1026 = SUBREG_TO_REG 0, %reg1024, 4 into this: %reg1025 = <sext> %reg1024 ... %reg1027 = EXTRACT_SUBREG %reg1025, 4 %reg1026 = SUBREG_TO_REG 0, %reg1027, 4 The problem here is that SUBREG_TO_REG is there to assert that an implicit zext occurs. It doesn't insert a zext instruction. If we allow the EXTRACT_SUBREG here, it will give us the value after the <sext>, not the original value of %reg1024 before <sext>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105741 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09Add argument name comments.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105665 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-07Fix a mistake in my previous change r105437: don't access operand 2 and assumeBob Wilson
that it is an immediate before checking that the instruction is an EXTRACT_SUBREG. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105585 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-07Add some basic debug output.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105561 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-07Cleanup. Process the dbg_values separatelyJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105554 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-07Move exit check where it really belongs.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105541 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-05Revert 105492 & 105493 due to a testcase regression. Radar 7424645.Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105511 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-05Fix some liveout handling related to tail calls, see comments.Dale Johannesen
I don't think this ever resulted in problems on x86, but it would on ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105509 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04Re-apply 105308 with fix.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105502 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04Make if-conversion ignore dbg_value instructions in its analysis. rdar://7797940Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105498 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04Support for nested functions/classes in debug output. Radar 7424645.Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105492 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04Skip dbg_value instructions when scanning instructions in register scavenging.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04Keep track of the call instructions whose clobber lists were skipped during fastJakob Stoklund Olesen
register allocation. Process all of the clobber lists at the end of the function, marking the registers as used in MachineRegisterInfo. This is necessary in case the calls clobber callee-saved registers (sic). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105473 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04Fixed a bug during widening where we would avoid legalizing a node. When weMon P Wang
replace an OpA with a widened OpB, it is possible to get new uses of OpA due to CSE when recursively updating nodes. Since OpA has been processed, the new uses are not examined again. The patch checks if this occurred and it it did, updates the new uses of OpA to use OpB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03Add some missing checks in TwoAddressInstructionPass::CoalesceExtSubRegs.Bob Wilson
Check that all the instructions are in the same basic block, that the EXTRACT_SUBREGs write to the same subregs that are being extracted, and that the source and destination registers are in the same regclass. Some of these constraints can be relaxed with a bit more work. Jakob suggested that the loop that checks for subregs when NewSubIdx != 0 should use the "nodbg" iterator, so I made that change here, too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105437 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03Cleanup 80-column and trim trailing whitespaceJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03Fix SimplifyDemandedBits' AssertZext logic to demand all the bits. ItDan Gohman
needs to demand the high bits because it's asserting that they're zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105406 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03Revert 105308.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105399 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03Machine sink could potentially sink instructions into a block where the physicalBill Wendling
registers it defines then interfere with an existing preg live range. For instance, if we had something like these machine instructions: BB#0 ... = imul ... EFLAGS<imp-def,dead> test ..., EFLAGS<imp-def> jcc BB#2 EFLAGS<imp-use> BB#1 ... ; fallthrough to BB#2 BB#2 ... ; No code that defines EFLAGS jcc ... EFLAGS<imp-use> Machine sink will come along, see that imul implicitly defines EFLAGS, but because it's "dead", it assumes that it can move imul into BB#2. But when it does, imul's "dead" imp-def of EFLAGS is raised from the dead (a zombie) and messes up the condition code for the jump (and pretty much anything else which relies upon it being correct). The solution is to know which pregs are live going into a basic block. However, that information isn't calculated at this point. Nor does the LiveVariables pass take into account non-allocatable physical registers. In lieu of this, we do a *very* conservative pass through the basic block to determine if a preg is live coming out of it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03One underscore, not two.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105379 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03Implement expansion in type legalization for add/sub with overflow. TheEli Friedman
expansion is the same as that used by LegalizeDAG. The resulting code sucks in terms of performance/codesize on x86-32 for a 64-bit operation; I haven't looked into whether different expansions might be better in general. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105378 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03Use the fast register allocator by default for -O0 builds.Jakob Stoklund Olesen
This affects both llvm-gcc and clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105372 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03Use readsWritesVirtualRegister instead of counting uses and defs when insertingJakob Stoklund Olesen
spills and reloads. This means that a partial define of a register causes a reload so the other parts of the register are preserved. The reload can be prevented by adding an <imp-def> operand for the full register. This is already done by the coalescer and live interval analysis where relevant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105369 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02Add full register <imp-def> operands when the coalescer is creating partialJakob Stoklund Olesen
register updates. These operands tell the spiller that the other parts of the partially defined register are don't-care, and a reload is not necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105361 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02Compulsive reformating. No functionalitical changes.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105359 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02Slightly change the meaning of the reMaterialize target hook when the originalJakob Stoklund Olesen
instruction defines subregisters. Any existing subreg indices on the original instruction are preserved or composed with the new subreg index. Also substitute multiple operands mentioning the original register by using the new MachineInstr::substituteRegister() function. This is necessary because there will soon be <imp-def> operands added to non read-modify-write partial definitions. This instruction: %reg1234:foo = FLAP %reg1234<imp-def> will reMaterialize(%reg3333, bar) like this: %reg3333:bar-foo = FLAP %reg333:bar<imp-def> Finally, replace the TargetRegisterInfo pointer argument with a reference to indicate that it cannot be NULL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02Remove the TargetRegisterClass member from CalleeSavedInfoRafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105344 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02Skip identical instruction while calculating DBG_VALUE range.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105340 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02Rename canCombinedSubRegIndex method to something more grammatically correctBob Wilson
and tidy up the comment describing it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105339 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02Use local small vector.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105332 91177308-0d34-0410-b5e6-96231b3b80d8
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