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2011-01-28Revert r124462. There are a few big regressions that I need to fix first.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124478 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-28Fix build with stdcxx by using llvm::next. Patch by Joerg Sonnenberger!Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124472 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-28Print the visibility of declarations.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124468 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-28- Stop simplifycfg from duplicating "ret" instructions into unconditionalEvan Cheng
branches. PR8575, rdar://5134905, rdar://8911460. - Allow codegen tail duplication to dup small return blocks after register allocation is done. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124462 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-27Remove a temporary workaround for a lencod miscompile. Depends on the fix in ↵Andrew Trick
r124442. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124443 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-27VirtRegRewriter fix: update kill flags, which are used by the scavenger.Andrew Trick
rdar://problem/8893967: JM/lencod miscompile at -arch armv7 -mthumb -O3 Added ResurrectKill to remove kill flags after we decide to reused a physical register. And (hopefully) ensure that we call it in all the right places. Sorry, I'm not checking in a unit test given that it's a miscompile I can't reproduce easily with a toy example. Failures in the rewriter depend on a series of heuristic decisions maked during one of the many upstream phases in codegen. This case would require coercing regalloc to generate a couple of rematerialzations in a way that causes the scavenger to reuse the same register at just the wrong point. The general way to test this is to implement kill flags verification. Then we could have a simple, robust compile-only unit test. That would be worth doing if the whole pass was not about to disappear. At this point we focus verification work on the next generation of regalloc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124442 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-27Speculatively revert r124380.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124397 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-27While legalizing SDValues do not drop SDDbgValues, trasfer them to new legal ↵Devang Patel
nodes. Take 2. This includes fix for dragonegg crash. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124380 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-27Avoid modifying the OneClassForEachPhysReg map while iterating over it.Bob Wilson
Linear scan regalloc is currently assuming that any register aliased with a member of a regclass must also be in at least one regclass. That is not always true. For example, for X86, RIP is in a regclass but IP is not. If you're unlucky, this can cause a crash by invalidating the iterator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124365 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-27Try harder to not have unused variables.Matt Beaumont-Gay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124350 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-27Opt-mode -Wunused-variable cleanupMatt Beaumont-Gay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124346 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-27Reapply 124301Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124339 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26Initialize variable to get rid of clang warning.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124331 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26Revert 124301.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124327 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26Revert r124302Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26[AVX] Add INSERT_SUBVECTOR and support it on x86. This provides aDavid Greene
default implementation for x86, going through the stack in a similr fashion to how the codegen implements BUILD_VECTOR. Eventually this will get matched to VINSERTF128 if AVX is available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124307 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26While legalizing SDValues do not drop SDDbgValues, trasfer them to new legal ↵Devang Patel
nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124302 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26Process valid SDDbgValues even if the node does not have any order assigned.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124301 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26Refactor.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124300 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26[AVX] Support EXTRACT_SUBVECTOR on x86. This provides a defaultDavid Greene
implementation of EXTRACT_SUBVECTOR for x86, going through the stack in a similr fashion to how the codegen implements BUILD_VECTOR. Eventually this will get matched to VEXTRACTF128 if AVX is available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124292 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26Rename member variables to follow the rest of LLVM.Jakob Stoklund Olesen
No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124257 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-25Provide an interface to transfer SDDbgValue from one SDNode to another.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124245 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-25Resolve DanglingDbgValue of PHI nodes where the use follows dbg.value ↵Devang Patel
intrinisic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124203 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-25This assertion is too restrictive, it does not apply for dangling dbg value ↵Devang Patel
nodes (nodes where dbg.value intrinsic preceds use of the value). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124202 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-24Support printing exception section into the current one. This is the case ↵Anton Korobeynikov
when LSDASection is blank git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124150 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-24Speculatively revert r124138.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124142 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-24Resolve DanglingDbgValue of PHI nodes where the use follows dbg.value ↵Devang Patel
intrinisic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124138 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-24Temporarily workaround JM/lencod miscompile (SIGSEGV).Andrew Trick
rdar://problem/8893967 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124137 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-23Add support for the --noexecstack option.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124077 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-23Null initialize a few variables flagged byTed Kremenek
clang's -Wuninitialized-experimental warning. While these don't look like real bugs, clang's -Wuninitialized-experimental analysis is stricter than GCC's, and these fixes have the benefit of being general nice cleanups. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124073 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-23Delay the creation of eh_frame so that the user can change the defaults.Rafael Espindola
Add support for SHT_X86_64_UNWIND. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-23Remove more duplicated code.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124056 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-23Remove duplicated code.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124054 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21Enable support for precise scheduling of the instruction selectionAndrew Trick
DAG. Disable using "-disable-sched-cycles". For ARM, this enables a framework for modeling the cpu pipeline and counting stalls. It also activates several heuristics to drive scheduling based on the model. Scheduling is inherently imprecise at this stage, and until spilling is improved it may defeat attempts to schedule. However, this framework provides greater control over tuning codegen. Although the flag is not target-specific, it should have very little affect on the default scheduler used by x86. The only two changes that affect x86 are: - scheduling a high-latency operation bumps the current cycle so independent operations can have their latency covered. i.e. two independent 4 cycle operations can produce results in 4 cycles, not 8 cycles. - Two operations with equal register pressure impact and no latency-based stalls on their uses will be prioritized by depth before height (height is irrelevant if no stalls occur in the schedule below this point). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123971 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21Convert -enable-sched-cycles and -enable-sched-hazard to -disableAndrew Trick
flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20SplitKit requires that all defs are in place before calling useIntv().Jakob Stoklund Olesen
The value mapping gets confused about which original values have multiple new definitions so they may need phi insertions. This could probably be simplified by letting enterIntvBefore() take a live range to be added following the instruction. As long as the range stays inside the same basic block, value mapping shouldn't be a problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123926 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Add LiveIntervalMap::dumpCache() to print out the cache used by the ssa ↵Jakob Stoklund Olesen
update algorithm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123925 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20My editor's indent went crazy. Fix.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123909 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Expand invalid return values for umulo and smulo. Handle these similarlyEric Christopher
to add/sub by doing the normal operation and then checking for overflow afterwards. This generally relies on the DAG handling the later invalid operations as well. Fixes the 64-bit part of rdar://8622122 and rdar://8774702. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123908 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Sorry, several patches in one.Evan Cheng
TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123905 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Selection DAG scheduler register pressure heuristic fixes.Andrew Trick
Added a check for already live regs before claiming HighRegPressure. Fixed a few cases of checking the wrong number of successors. Added some tracing until these heuristics are better understood. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123892 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Check that a live range exists before shortening it. This fixes PR8989.Jakob Stoklund Olesen
The live range may have been deleted earlier because of rematerialization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123891 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Add hidden -verify-coalescing to run the machine code verifier before and afterJakob Stoklund Olesen
register coalescing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123890 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Fix bug found by new clang warning.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123872 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Use only one API at a time.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123866 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20If we can, lower the multiply part of a umulo/smulo call to a libcallEric Christopher
with an invalid type then split the result and perform the overflow check normally. Fixes the 32-bit parts of rdar://8622122 and rdar://8774702. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123864 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Fix debug info for merged global.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123862 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-19Divert Hopfield network debug output. It is very noisy.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123859 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-19Don't accidentally leave small gaps in the live ranges when leaving the activeJakob Stoklund Olesen
interval after an instruction. The leaveIntvAfter() method only adds liveness from the instruction's boundary index to the inserted copy. Ideally, SplitKit should be smarter about this, perhaps by combining useIntv() and leaveIntvAfter() into one method that guarantees continuity. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123858 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-19Fix register address expression. Patch by Ken Dyck.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123856 91177308-0d34-0410-b5e6-96231b3b80d8
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