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The argument is unused, and is a layering violation in any case.
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uses of getCompileUnit().
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possible.
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variable.
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location expressions. In such cases, AT_location attribute's value will be a label.
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instruction.
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When a variable is inlined multiple places, abstract variable keeps name, location, type etc.. info and all other concreate instances of the variable directly refers to abstract variable.
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create new global variable.
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new subprogram.
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be illegal, even if the requested vector type is legal. Testcase is one of the
disabled ARM tests in the vector-select patch.
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This implements the 'landingpad' instruction. It's used to indicate that a basic
block is a landing pad. There are several restrictions on its use (see
LangRef.html for more detail). These restrictions allow the exception handling
code to gather the information it needs in a much more sane way.
This patch has the definition, implementation, C interface, parsing, and bitcode
support in it.
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when building with assertions disabled.
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This is possible now that we now longer provide an interface to iterate
the interference overlaps.
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The Query class now holds two iterators instead of an InterferenceResult
instance. The iterators are used as bookmarks for repeated
collectInterferingVRegs calls.
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collectInterferingVRegs will be the primary function for interference
checks.
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No clients are iterating over interference overlaps.
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The InterferenceResult iterator turned out to be less important than we
thought it would be. LiveIntervalUnion clients want higher level
information, like the list of interfering virtual registers.
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lower XMM register gets in first. This will allow the SUBREG pattern to
elliminate the first vector insertion.
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It's somewhat surprising anything works without this. Before we would
compile the testcase into:
test: # @test
movl $4, 8(%rdi)
movl 8(%rdi), %eax
orl %esi, %eax
cmpl $32, %edx
movl %eax, -4(%rsp) # 4-byte Spill
je .LBB0_2
now we produce:
test: # @test
movl 8(%rdi), %eax
movl $4, 8(%rdi)
orl %esi, %eax
cmpl $32, %edx
movl %eax, -4(%rsp) # 4-byte Spill
je .LBB0_2
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also. There is no point extending debug variable out side its lexical block. This provides 6x compile time speedup in some cases.
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instructions.
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Coalescing can remove copy-like instructions with sub-register operands
that constrained the register class. Examples are:
x86: GR32_ABCD:sub_8bit_hi -> GR32
arm: DPR_VFP2:ssub0 -> DPR
Recompute the register class of any virtual registers that are used by
less instructions after coalescing.
This affects code generation for the Cortex-A8 where we use NEON
instructions for f32 operations, c.f. fp_convert.ll:
vadd.f32 d16, d1, d0
vcvt.s32.f32 d0, d16
The register allocator is now free to use d16 for the temporary, and
that comes first in the allocation order because it doesn't interfere
with any s-registers.
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This function doesn't have anything to do with spill weights, and MRI
already has functions for manipulating the register class of a virtual
register.
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No functional change.
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RegisterCoalescer.h still has the CoalescerPair class interface.
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A public interface is no longer needed since RegisterCoalescer is not an
analysis any more.
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These the methods are target-independent since they simply scan the
memory operands. They can live in TargetInstrInfoImpl.
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All new local ranges are marked as RS_New now, so there is no need to
attempt splitting of RS_Spill ranges any more.
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The local ranges created get to stay in the RS_New stage, just like for
local and region splitting.
This gives tryLocalSplit a bit more freedom the first time it sees one
of these new local ranges.
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