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2011-10-12Add MachineInstr::getRegClassConstraint().Jakob Stoklund Olesen
Most instructions have some requirements for their register operands. Usually, this is expressed as register class constraints in the MCInstrDesc, but for inline assembly the constraints are encoded in the flag words. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141835 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Extract a method for finding the inline asm flag operand.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141834 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Encode register class constreaints in inline asm instructions.Jakob Stoklund Olesen
The inline asm operand constraint is initially encoded in the virtual register for the operand, but that register class may change during coalescing, and the original constraint is lost. Encode the original register class as part of the flag word for each inline asm operand. This makes it possible to recover the actual constraint required by inline asm, just like we can for normal instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141833 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12We need to verify that the machine instruction we're using as a replacement forBill Wendling
our current machine instruction defines a register with the same register class as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it would ICE because a tail call was expecting one register class but was given another. (The machine instruction verifier catches this situation.) <rdar://problem/10270968> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141830 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Use a utility from MathExtras to clarify a check and avoid undefined ↵Eli Friedman
behavior. Based on patch by Ahmed Charles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141829 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Disable machine LICM speculation check (for profitability) until I have time ↵Evan Cheng
to investigate the regressions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141813 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12To find the exiting VN of a LiveInterval from a block, use the previous slotCameron Zwarich
rather than the previous index. If a block has a single instruction, the previous index may be in a different basic block. I have no clue how this used to work on all of test-suite, because now this failure is seen quite often when trying to compile code with -strong-phi-elim. This fixes PR10252. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141812 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Fix a thinko that Nick noticed. The previous code actually worked asDan Gohman
intended, but only by accident. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141779 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Expand the check for a landing pad so that it looks at the basic block'sBill Wendling
containing loop's header to see if that's a landing pad. If it is, then we don't want to hoist instructions out of the loop and above the header. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141767 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Use an existing function.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141763 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Fix r141744.Evan Cheng
1. The speculation check may not have been performed if the BB hasn't had a load LICM candidate. 2. If the candidate would be CSE'ed, then go ahead and speculatively LICM the instruction even if it's in high register pressure situation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141747 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Refine r141689 with a tri-state variable.Evan Cheng
Also teach MachineLICM to avoid "speculation" when register pressure is high. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141744 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Add a new wrapper node for a DILexicalBlock that encapsulates it and aEric Christopher
file. Since it should only be used when necessary propagate it through the backend code generation and tweak testcases accordingly. This helps with code like in clang's test/CodeGen/debug-info-line.c where we have multiple #line directives within a single lexical block and want to generate only a single block that contains each file change. Part of rdar://10246360 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141729 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Formatting.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141728 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11N.B. This is with the new EH scheme:Bill Wendling
The blocks with invokes have branches to the dispatch block, because that more correctly models the behavior of the CFG. The dispatch of course has edges to the landing pads. Those landing pads could contain invokes, which then have branches back to the dispatch. This creates a loop. The machine LICM pass looks at this loop and thinks it can hoist elements out of it. But because the dispatch is an alternate entry point into the program, the hoisted instructions won't be executed. I wasn't able to get a testcase which was small and could reproduce all of the time. The function_try_block.cpp in llvm-test was where this showed up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141726 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Add dominance check for the instruction being hoisted.Devang Patel
For example, MachineLICM should not hoist a load that is not guaranteed to be executed. Radar 10254254. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Add support for legalization of vector SHL/SRA/SRL instructionsNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141667 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Add support for legalization of vector trunc-store where the saved scalar ↵Nadav Rotem
type is illegal (for example, v2i16 on systems where the smallest store size is i32) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141661 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Cleanup the trunc-store legalization code and add asserts.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141659 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10Revert r141569 and r141576.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141594 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10Give targets a chance to expand even standard pseudos.Jakob Stoklund Olesen
Allow targets to expand COPY and other standard pseudo-instructions before they are expanded with copyPhysReg(). This allows the target to examine the COPY instruction for extra operands indicating it can be widened to a preferable super-register copy. See the ARM -widen-vmovs option. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141578 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10If loop header is also loop exiting block then it may not be safe to hoist ↵Devang Patel
instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141576 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10Add dominance check for the instruction being hoisted.Devang Patel
For example, MachineLICM should not hoist a load that is not guaranteed to be executed. Radar 10254254. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08Use the code that lowers the arguments and spills any values which are aliveBill Wendling
across unwind edges. This is for the back-end which expects such things. The code is from the original SjLj EH pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141463 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented toBill Wendling
do. This will be useful later on with the new SJLJ stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141416 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07PostRA scheduler fix. Clear stale loop dependencies.Andrew Trick
Fixes <rdar://problem/10235725> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141357 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141356 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06Remove the old atomic instrinsics. autoupgrade functionality is included ↵Eli Friedman
with this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141333 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Modify the mapping from landing pad to call sites to accept more than one callBill Wendling
site. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141226 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Add an ivar that maps a landing pad's EH symbol to the call sites that may jumpBill Wendling
to the landing pad. This will be used by the back-end to generate the jump tables for dispatching the arriving longjmp in sjlj eh. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141224 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Small refactoring. Cache the FunctionInfo->MBB into a local variable.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141221 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Fix sub-register operand verification.Jakob Stoklund Olesen
PhysReg operands are not allowed to have sub-register indices at all. For virtual registers with sub-reg indices, check that all registers in the register class support the sub-reg index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141220 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Fix comment to reflect the new EH stuff.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141218 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Remove unused DstSubIdx argument.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141214 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Simplify EXTRACT_SUBREG emission.Jakob Stoklund Olesen
EXTRACT_SUBREG is emitted as %dst = COPY %src:sub, so there is no need to constrain the %dst register class. RegisterCoalescer will apply the necessary constraints if it decides to eliminate the COPY. The %src register class does need to be constrained to something with the right sub-registers, though. This is currently done manually with COPY_TO_REGCLASS nodes. They can possibly be removed after this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141207 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Simplify INSERT_SUBREG emission.Jakob Stoklund Olesen
The register class created by INSERT_SUBREG and SUBREG_TO_REG must be legal and support the SubIdx sub-registers. The new getSubClassWithSubReg() hook can compute that. This may create INSERT_SUBREG instructions defining a larger register class than the sub-register being inserted. That is OK, RegisterCoalescer will constrain the register class as needed when it eliminates the INSERT_SUBREG instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141198 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Add a FIXME.Jakob Stoklund Olesen
TwoAddressInstructionPass should annotate instructions with <undef> flags when it lower REG_SEQUENCE instructions. LiveIntervals should not be in the business of modifying code (except for kill flags, perhaps). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141187 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Also add <imp-use,kill> flags for redefined super-registers.Jakob Stoklund Olesen
For example: %vreg10:dsub_0<def,undef> = COPY %vreg1 %vreg10:dsub_1<def> = COPY %vreg2 is rewritten as: %D2<def> = COPY %D0, %Q1<imp-def> %D3<def> = COPY %D1, %Q1<imp-use,kill>, %Q1<imp-def> The first COPY doesn't care about the previous value of %Q1, so it doesn't read that register. The second COPY is a partial redefinition of %Q1, so it implicitly kills and redefines that register. This makes it possible to recognize instructions that can harmlessly clobber the full super-register. The write and don't read the super-register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141139 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Also add <def,undef> flags when coalescing sub-registers.Jakob Stoklund Olesen
RegisterCoalescer can create sub-register defs when it is joining a register with a sub-register. Add <undef> flags to these new sub-register defs where appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141138 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04Teach the MC to output code/data region marker labels in MachO and ELF ↵Owen Anderson
modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141135 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04Create a mapping between the landing pad basic block and the call site index ↵Bill Wendling
for later use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04Allow <undef> flags on def operands as well as uses.Jakob Stoklund Olesen
The <undef> flag says that a MachineOperand doesn't read its register, or doesn't depend on the previous value of its register. A full register def never depends on the previous register value. A partial register def may depend on the previous value if it is intended to update part of a register. For example: %vreg10:dsub_0<def,undef> = COPY %vreg1 %vreg10:dsub_1<def> = COPY %vreg2 The first copy instruction defines the full %vreg10 register with the bits not covered by dsub_0 defined as <undef>. It is not considered a read of %vreg10. The second copy modifies part of %vreg10 while preserving the rest. It has an implicit read of %vreg10. This patch adds a MachineOperand::readsReg() method to determine if an operand reads its register. Previously, this was modelled by adding a full-register <imp-def> operand to the instruction. This approach makes it possible to determine directly from a MachineOperand if it reads its register. No scanning of MI operands is required. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141124 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04Generic cleanup.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141050 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03Don't carry over the dispatchsetup hack from the old system.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141040 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03Move the grabbing of the jump buffer into the caller function, eliminating ↵Bill Wendling
the need for returning a std::pair. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03Whitespace.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141005 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03Typo.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01Moved type construction out of the loop and added an assert on the legality ↵Nadav Rotem
of the type. Formatted lines to the 80 char limit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140952 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30When inferring the pointer alignment, if the global doesn't have an initializerBill Wendling
and the alignment is 0 (i.e., it's defined globally in one file and declared in another file) it could get an alignment which is larger than the ABI allows for that type, resulting in aligned moves being used for unaligned loads. For instance, in file A.c: struct S s; In file B.c: struct { // something long }; extern S s; void foo() { struct S p = s; // ... } this copy is a 'memcpy' which is turned into a series of 'movaps' instructions on X86. But this is wrong, because 'struct S' has alignment of 4, not 16. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140902 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30Promote comment to doxycomment. Adjust whitespace. No functionality change.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140899 91177308-0d34-0410-b5e6-96231b3b80d8
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