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2012-01-15DAGCombiner: Deduplicate code.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148217 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-15Truncate of undef is just undef of smaller size.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148205 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-14Speculatively revert commit 148175 (rafael), to see if this fixesDuncan Sands
non-determinism in the 32 bit dragonegg buildbot. Original commit message: Only emit the Leh_func_endN symbol when needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148191 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-14Only emit the Leh_func_endN symbol when needed.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148175 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-14misched: Initial code for building an MI level scheduling DAGAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148174 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-14Move physreg dependency generation into aptly named addPhysRegDeps.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148173 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-14misched: Added ScheduleDAGInstrs::IsPostRAAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148172 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-14misched: Invoke the DAG builder on each sequence of schedulable instructions.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148171 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-14Move things around to make the file navigable, even though it will probably ↵Andrew Trick
be split up later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148170 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-14After r147827 and r147902, it's now possible for unallocatable registers to beEvan Cheng
live across BBs before register allocation. This miscompiled 197.parser when a cmp + b are optimized to a cbnz instruction even though the CPSR def is live-in a successor. cbnz r6, LBB89_12 ... LBB89_12: ble LBB89_1 The fix consists of two parts. 1) Teach LiveVariables that some unallocatable registers might be liveouts so don't mark their last use as kill if they are. 2) ARM constantpool island pass shouldn't form cbz / cbnz if the conditional branch does not kill CPSR. rdar://10676853 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148168 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13Remove previous commit while I debug the bot failures.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148156 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13Remove label that is not used anymore.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148150 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13Remove pointless mode line in .cpp file.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148143 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13Added the MachineSchedulerPass skeleton.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148105 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13wrong filenameAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148103 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-1380-col violationAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148102 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13DAGCombine's logic for forming pre- and post- indexed loads / stores were beingEvan Cheng
overly conservative. It was concerned about cases where it would prohibit folding simple [r, c] addressing modes. e.g. ldr r0, [r2] ldr r1, [r2, #4] => ldr r0, [r2], #4 ldr r1, [r2] Change the logic to look for such cases which allows it to form indexed memory ops more aggressively. rdar://10674430 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148086 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12Revert accidental commit.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148065 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12Fix the code that was WRONG.Bill Wendling
The registers are placed into the saved registers list in the reverse order, which is why the original loop was written to loop backwards. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148064 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12Added FPOW, FEXP, FLOG to PromoteNode so that custom actions can be set to ↵Pete Cooper
Promote for those operations. Sorry, no test case yet git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148050 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12When hoisting common code, watch out for uses which are marked "kill". If theEvan Cheng
killed registers are needed below the insertion point, then unset the kill marker. Sorry I'm not able to find a reduced test case. rdar://10660944 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148043 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12Allow targets to select source order pre-RA scheduler.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148033 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12Make SplitAnalysis::UseSlots private.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148031 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11Make data structures private.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147979 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11Sink spillInterferences into RABasic.Jakob Stoklund Olesen
This helper method is too simplistic for RAGreedy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147976 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11Cleanup.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147975 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11Move RegAllocBase into its own cpp file separate from RABasic.Jakob Stoklund Olesen
No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147972 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11On AVX, we can load v8i32 at a time. The bug happens when two uneven loads ↵Nadav Rotem
are used. When we load the v12i32 type, the GenWidenVectorLoads method generates two loads: v8i32 and v4i32 and attempts to use CONCAT_VECTORS to join them. In this fix I concat undef values to widen the smaller value. The test "widen_load-2.ll" also exposes this bug on AVX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147964 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11Teach the X86 instruction selection to do some heroic transforms toChandler Carruth
detect a pattern which can be implemented with a small 'shl' embedded in the addressing mode scale. This happens in real code as follows: unsigned x = my_accelerator_table[input >> 11]; Here we have some lookup table that we look into using the high bits of 'input'. Each entity in the table is 4-bytes, which means this implicitly gets turned into (once lowered out of a GEP): *(unsigned*)((char*)my_accelerator_table + ((input >> 11) << 2)); The shift right followed by a shift left is canonicalized to a smaller shift right and masking off the low bits. That hides the shift right which x86 has an addressing mode designed to support. We now detect masks of this form, and produce the longer shift right followed by the proper addressing mode. In addition to saving a (rather large) instruction, this also reduces stalls in Intel chips on benchmarks I've measured. In order for all of this to work, one part of the DAG needs to be canonicalized *still further* than it currently is. This involves removing pointless 'trunc' nodes between a zextload and a zext. Without that, we end up generating spurious masks and hiding the pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147936 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11Detect when a value is undefined on an edge to a landing pad.Jakob Stoklund Olesen
Consider this code: int h() { int x; try { x = f(); g(); } catch (...) { return x+1; } return x; } The variable x is undefined on the first edge to the landing pad, but it has the f() return value on the second edge to the landing pad. SplitAnalysis::getLastSplitPoint() would assume that the return value from f() was live into the landing pad when f() throws, which is of course impossible. Detect these cases, and treat them as if the landing pad wasn't there. This allows spill code to be inserted after the function call to f(). <rdar://problem/10664933> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147912 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11Exclusively use SplitAnalysis::getLastSplitPoint().Jakob Stoklund Olesen
Delete the alternative implementation in LiveIntervalAnalysis. These functions computed the same thing, but SplitAnalysis caches the result. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147911 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11Avoid CSE of instructions which define physical registers across MBBs unlessEvan Cheng
the physical registers are not allocatable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-1080 col violation.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147884 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Add 'llvm_unreachable' to passify GCC's understanding of the constraintsChandler Carruth
of several newly un-defaulted switches. This also helps optimizers (including LLVM's) recognize that every case is covered, and we should assume as much. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147861 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Remove unnecessary default cases in switches that cover all enum values.David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147855 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Fix a bug in the legalization of shuffle vectors. When we emulate shuffles ↵Nadav Rotem
using BUILD_VECTORS we may be using a BV of different type. Make sure to cast it back. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147851 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Allow machine-cse to look across MBB boundary when cse'ing instructions thatEvan Cheng
define physical registers. It's currently very restrictive, only catching cases where the CE is in an immediate (and only) predecessor. But it catches a surprising large number of cases. rdar://10660865 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147827 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Remove the logging streamer.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147820 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-08Avoid eraseing copies from a reserved register unless the definition can beEvan Cheng
safely proven not to have been clobbered. No small test case possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147751 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07Replace some uses of hasNUsesOfValue(0, X) with !hasAnyUseOfValue(X)Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147733 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07Add some DAG combines for SUBC/SUBE. If nothing uses the carry/borrow out of ↵Craig Topper
subc, turn it into a sub. Turn (subc x, x) into 0 with no borrow. Turn (subc x, 0) into x with no borrow. Turn (subc -1, x) into (xor x, -1) with no borrow. Turn sube with no borrow in into subc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147728 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07Optimize reserved register coalescing.Jakob Stoklund Olesen
Reserved registers don't have proper live ranges, their LiveInterval simply has a snippet of liveness for each def. Virtual registers with a single value that is a copy of a reserved register (typically %esp) can be coalesced with the reserved register if the live range doesn't overlap any reserved register defs. When coalescing with a reserved register, don't modify the reserved register live range. Just leave it as a bunch of dead defs. This eliminates quadratic coalescer behavior in i386 functions with many function calls. PR11699 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147726 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07Use the 'regalloc' debug tag for most register allocator tracing.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147725 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07Revert part of r147716. Looks like x87 instructions kill markers are all messedEvan Cheng
up so branch folding pass can't use the scavenger. :-( This doesn't breaks anything currently. It just means targets which do not carefully update kill markers cannot run post-ra scheduler (not new, it has always been the case). We should fix this at some point since it's really hacky. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147719 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07Added a late machine instruction copy propagation pass. This catchesEvan Cheng
opportunities that only present themselves after late optimizations such as tail duplication .e.g. ## BB#1: movl %eax, %ecx movl %ecx, %eax ret The register allocator also leaves some of them around (due to false dep between copies from phi-elimination, etc.) This required some changes in codegen passes. Post-ra scheduler and the pseudo-instruction expansion passes have been moved after branch folding and tail merging. They were before branch folding before because it did not always update block livein's. That's fixed now. The pass change makes independently since we want to properly schedule instructions after branch folding / tail duplication. rdar://10428165 rdar://10640363 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147716 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07Missing raw_ostream.h breaks MSVC build.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147703 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-06Add comment.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147696 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-06Add a comment and ensure that anyone else looking at this code doesn't startEric Christopher
to bleed from the eyes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147695 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-06Use const vector references instead of a vector copy. Spotted by Devang.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147694 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-06Use -> instead of (*iter).Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147693 91177308-0d34-0410-b5e6-96231b3b80d8
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