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2012-01-24Set correct <def,undef> flags when lowering REG_SEQUENCE.Jakob Stoklund Olesen
A REG_SEQUENCE instruction is lowered into a sequence of partial defs: %vreg7:ssub_0<def,undef> = COPY %vreg20:ssub_0 %vreg7:ssub_1<def> = COPY %vreg2 %vreg7:ssub_2<def> = COPY %vreg2 %vreg7:ssub_3<def> = COPY %vreg2 The first def needs an <undef> flag to indicate it is the beginning of the live range, while the other defs are read-modify-write. Previously, we depended on LiveIntervalAnalysis to notice and fix the missing <def,undef>, but that solution was never robust, it was causing problems with ProcessImplicitDefs and the lowering of chained REG_SEQUENCE instructions. This fixes PR11841. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148879 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Use the standard MachineFunction::print() after SlotIndexes.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148878 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Fix old doxygen comment.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148825 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24add more support for ConstantDataSequentialChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148802 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24An option to selectively enable part of ARM EHABI support.Evgeniy Stepanov
This change adds an new option --arm-enable-ehabi-descriptors that enables emitting unwinding descriptors. This provides a mode with a working backtrace() without the (currently broken) exception support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148800 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Bit pack DIE structures better.Benjamin Kramer
16 bits are sufficient to store attributes, tags and forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148799 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Remove generation of DW_AT_sibling. Nothing as far as I can tell uses it.Eric Christopher
Saves about 1.5% on debug info size. rdar://10278198 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148794 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Add AsmPrinter (aka MCLowering) support for ConstantDataSequential, Chris Lattner
and clean up some other misc stuff. Unlike ConstantArray, we will prefer to emit .fill directives for "String" arrays that all have the same value, since they are denser than emitting a .ascii git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148793 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Preserve <def,undef> flags in CoalesceExtSubRegs.Jakob Stoklund Olesen
This won't have an effect until EliminateRegSequences() starts setting the undef flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148779 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Revert r148686 (and r148694, a fix to it) due to a serious layeringChandler Carruth
violation -- MC cannot depend on CodeGen. Specifically, the MCTargetDesc component of each target is actually a subcomponent of the MC library. As such, it cannot depend on the target-independent code generator, because MC itself cannot depend on the target-independent code generator. This change moved a flag from the ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in ARMException.cpp, leaving behind an 'extern' to refer back to it. That layering order isn't viable givin the constraints outlined above. Commandline flags are designed to be static specifically to avoid these types of bugs. Fixing this is likely going to require some non-trivial refactoring. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148759 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23Remove extraneous ';'s.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148740 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23copyImplicitOps is redundant here - the loop above already copies these ops.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148725 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23Fix PR11829. PostRA LICM was too aggressive.Jakob Stoklund Olesen
This fixes a typo in r148589. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148724 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23Simplify debug output.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148723 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23An option to selectively enable parts of ARM EHABI support.Evgeniy Stepanov
This change adds an new value to the --arm-enable-ehabi option that disables emitting unwinding descriptors. This mode gives a working backtrace() without the (currently broken) exception support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148686 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-22Add an option to disable buggy copy propagation passAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148662 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-21Fix an obvious typo.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148622 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-21Handle register masks in LiveVariables.Jakob Stoklund Olesen
A register mask operand kills any live physreg that isn't preserved. Unlike an implicit-def operand, the clobbered physregs are never live afterwards. This means LiveVariables has to track a much smaller number of live physregs, and it should spend much less time in addRegisterDead(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148609 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20Delete an unused member variable.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148594 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20Support register masks in MachineLICM.Jakob Stoklund Olesen
Only PostRA LICM is affected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148589 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20Handle register masks in DeadMachineInstructionElim.Jakob Stoklund Olesen
Don't track live physregs that are clobbered by a register mask operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148588 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20More dead code removal (using -Wunreachable-code)David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20Extend Attributes to 64 bitsKostya Serebryany
Problem: LLVM needs more function attributes than currently available (32 bits). One such proposed attribute is "address_safety", which shows that a function is being checked for address safety (by AddressSanitizer, SAFECode, etc). Solution: - extend the Attributes from 32 bits to 64-bits - wrap the object into a class so that unsigned is never erroneously used instead - change "unsigned" to "Attributes" throughout the code, including one place in clang. - the class has no "operator uint64 ()", but it has "uint64_t Raw() " to support packing/unpacking. - the class has "safe operator bool()" to support the common idiom: if (Attributes attr = getAttrs()) useAttrs(attr); - The CTOR from uint64_t is marked explicit, so I had to add a few explicit CTOR calls - Add the new attribute "address_safety". Doing it in the same commit to check that attributes beyond first 32 bits actually work. - Some of the functions from the Attribute namespace are worth moving inside the class, but I'd prefer to have it as a separate commit. Tested: "make check" on Linux (32-bit and 64-bit) and Mac (10.6) built/run spec CPU 2006 on Linux with clang -O2. This change will break clang build in lib/CodeGen/CGCall.cpp. The following patch will fix it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148553 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20When lowering the 'resume' instruction, look to see if we can eliminate theBill Wendling
'insertvalue' instructions that recreate the structure returned by the 'landingpad' instruction. Because the 'insertvalue' instruction isn't supported by FastISel, this can save a bit of time during -O0 compilation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148520 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19More bundle related API additions.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148465 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19Rewriter should definitly rewrite instructions inside bundles.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148464 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19Enhance finalizeBundle to return end of bundle iterator because it makes sense.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148462 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19- Slight change to finalizeBundle() interface. LastMI is not exclusive (pointingEvan Cheng
to instruction right after the last instruction in the bundle. - Add a finalizeBundle() variant that doesn't specify LastMI. Instead, the code will find the last instruction in the bundle by following the 'InsideBundle' marker. This is useful in case bundles are formed early (i.e. during MI scheduling) but finalized later (i.e. after register allocator has finished rewriting virtual registers with physical registers). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148444 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19Rename Finalizebundle to finalizeBundle to conform to coding guideline.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148440 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Add a RegisterMaskSDNode class.Jakob Stoklund Olesen
This SelectionDAG node will be attached to call nodes by LowerCall(), and eventually becomes a MO_RegisterMask MachineOperand on the MachineInstr representing the call instruction. LowerCall() will attach a register mask that depends on the calling convention. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148436 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Fixed macro condition.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148408 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Fix a bug in the type-legalization of vector integers. When we bitcast one ↵Nadav Rotem
vector type to another, we must not bitcast the result if one type is widened while the other is promoted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148383 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Fix ISD::REG_SEQUENCE to accept physical registers and change ↵Pete Cooper
TwoAddressInstructionPass to insert copies for any physical reg operands of the REG_SEQUENCE git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148377 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148337 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17Teach DAG combiner to turn a BUILD_VECTOR of UNDEFs into an UNDEF of vector ↵Craig Topper
type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148297 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17misched: Inital interface and implementation for ScheduleTopDownLive and ↵Andrew Trick
ShuffleInstructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148291 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17Renamed MachineScheduler to ScheduleTopDownLive.Andrew Trick
Responding to code review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148290 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17Moving options declarations around.Andrew Trick
More short term hackery until we have a way to configure passes that work on LiveIntervals. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148289 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17Add 148175 back. I am unable to reproduce any non determinism in a dragoneggRafael Espindola
or clang bootstrap. I will keep an eye on the bots. Original message: Only emit the Leh_func_endN symbol when needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148283 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17Changed flag operand of ISD::FP_ROUND to TargetConstant as it should not get ↵Pete Cooper
checked for legalisation git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148275 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17Fix typo in comment.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148268 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16Removing unused default switch cases in switches over enums that already ↵David Blaikie
account for all enumeration values explicitly. (This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148262 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16AggressiveAntiDepBreaker needs to skip debug values because a debug value ↵Hal Finkel
does not have a corresponding SUnit git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148260 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16Extract method for detecting constant unallocatable physregs.Jakob Stoklund Olesen
It is safe to move uses of such registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148259 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16Give better scavenger errors by invoking the verifier.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148251 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16Add a new kind of MachineOperand: MO_RegisterMask.Jakob Stoklund Olesen
Register masks will be used as a compact representation of large clobber lists. Currently, an x86 call instruction has some 40 operands representing call-clobbered registers. That's more than 1kB of useless operands per call site. A register mask operand references a bit mask of call-preserved registers, everything else is clobbered. The bit mask will typically come from TargetRegisterInfo::getCallPreservedMask(). By abandoning ImplicitDefs for call-clobbered registers, it also becomes possible to share call instruction descriptions between calling conventions, and we can get rid of the WINCALL* instructions. This patch introduces the new operand kind. Future patches will add RegMask support to target-independent passes before finally the fixed clobber lists can be removed from call instruction descriptions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148250 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16Refactor variables unused under non-assert builds (& remove two entirely ↵David Blaikie
unused variables). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148230 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16Changed intrinsic ID operand to a target constant as its not used in any ↵Pete Cooper
arithmetic so should not be checked in legalisation git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148228 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-15[AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits.Nadav Rotem
We know that the blend instructions only use the MSB, so if the mask is sign-extended then we can convert it into a SHL instruction. This is a common pattern because the type-legalizer sign-extends the i1 type which is used by the LLVM-IR for the condition. Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148225 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-15Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through ↵Benjamin Kramer
CodeGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148218 91177308-0d34-0410-b5e6-96231b3b80d8
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