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2012-02-15reverting r150565. Premature push.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150566 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Move PostRAMachineLICM into MachineLateOptimization. It now runs after PEI!Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150565 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Allow CodeGen (llc) command line options to work as expected.Andrew Trick
The llc command line options for enabling/disabling passes are local to CodeGen/Passes.cpp. This patch associates those options with standard pass IDs so they work regardless of how the target configures the passes. A target has two ways of overriding standard passes: 1) Redefine the pass pipeline (override TargetPassConfig::add%Stage) 2) Replace or suppress individiual passes with TargetPassConfig::substitutePass. In both cases, the command line options associated with the pass override the target default. For example, say a target wants to disable machine instruction scheduling by default: - The target calls disablePass(MachineSchedulerID) but otherwise does not override any TargetPassConfig methods. - Without any llc options, no scheduler is run. - With -enable-misched, the standard machine scheduler is run and honors the -misched=... flag to select the scheduler variant, which may be used for performance evaluation or testing. Sorry overridePass is ugly. I haven't thought of a better way without replacing the cl::opt framework. I hope to do that one day... I haven't figured out why CodeGen uses char& for pass IDs. AnalysisID is much easier to use and less bug prone. I'm using it wherever I can for internal implementation. Maybe later we can change the global pass ID definitions as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150563 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Added TargetPassConfig::disablePass/substitutePass as a general mechanism to ↵Andrew Trick
override specific passes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150562 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Don't emit live ranges for physregs live-ins that are dead.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150553 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Disentangle moving a machine instr from updating LiveIntervals.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150552 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Added hook to let targets custom lower splitting of illegal vectorsPete Cooper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150550 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Fix global live range splitting regmask accuracy.Jakob Stoklund Olesen
Pretend that regmask interference ends at the 'dead' slot, even when there is other interference ending at the 'reg' slot of the same instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150531 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Fix details in local live range splitting with regmasks.Jakob Stoklund Olesen
Perform all comparisons at instruction granularity, and make sure register masks on uses count in both gaps. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150530 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Handle regmasks in findRegisterDefOperandIdx().Jakob Stoklund Olesen
Only accept register masks when looking for an 'overlapping' def. When Overlap is not set, the function searches for a proper definition of Reg. This means MI->modifiesRegister() considers register masks, but MI->definesRegister() doesn't. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150529 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Use the proper clobber check in handleLiveInRegister().Jakob Stoklund Olesen
When a physreg is live in to a basic block, look for any instruction in the block that clobbers the physreg. The instruction doesn't have to properly redefine the register, any overlapping clobber is OK. This slightly changes live ranges when compiling with register masks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150528 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Dump live intervals in numerical order.Jakob Stoklund Olesen
The old DenseMap hashed order was very confusing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150527 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Don't create a new copy of reserved regs - we already have one handy.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150525 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Add code to the target lowering object file module to handle module flags.Bill Wendling
The MachO back-end needs to emit the garbage collection flags specified in the module flags. This is a WIP, so the front-end hasn't been modified to emit these flags just yet. Documentation and front-end switching to occur soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150507 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Update MachineVerifier to check the new physreg live-in rules.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150496 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Tighten physical register invariants: Allocatable physical registers canLang Hames
only be live in to a block if it is the function entry point or a landing pad. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150494 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Fix PR12000. Some vector operations may use scalar operands with typesNadav Rotem
that are greater than the vector element type. For example BUILD_VECTOR of type <1 x i1> with a constant i8 operand. This patch fixes the assertion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150477 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Turn push_back loops into append/insert.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150471 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Rename getExceptionAddressRegister() to getExceptionPointerRegister() for ↵Lang Hames
consistency with setExceptionPointerRegister(...). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150460 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Use convenience function for consistency.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150457 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Don't reserve the R0 and R1 registers here. We don't use these registers, andBill Wendling
marking them as "live-in" into a BB ruins some invariants that the back-end tries to maintain. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150437 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Don't recalculate the size of the vector each time through the loop.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150436 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Add register mask support to ScheduleDAGRRList.Jakob Stoklund Olesen
The scheduler will sometimes check the implicit-def list on instructions to properly handle pre-colored DAG edges. Also check any register mask operands for physreg clobbers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150428 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13LiveIntervalAnalysis does not depend on MachineLoopInfo.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150411 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Check regmask interference for -join-physregs.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150404 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Fix a bug in DAGCombine for the optimization of BUILD_VECTOR. We cant ↵Nadav Rotem
generate a shuffle node from two vectors of different types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150383 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-12This patch addresses the problem of poor code generation for the zextNadav Rotem
v8i8 -> v8i32 on AVX machines. The codegen often scalarizes ANY_EXTEND nodes. The DAGCombiner has two optimizations that can mitigate the problem. First, if all of the operands of a BUILD_VECTOR node are extracted from an ZEXT/ANYEXT nodes, then it is possible to create a new simplified BUILD_VECTOR which uses UNDEFS/ZERO values to eliminate the scalar ZEXT/ANYEXT nodes. Second, another dag combine optimization lowers BUILD_VECTOR into a shuffle vector instruction. In the case of zext v8i8->v8i32 on AVX, a value in an XMM register is to be shuffled into a wide YMM register. This patch modifes the second optimization and allows the creation of shuffle vectors even when the newly generated vector and the original vector from which we extract the values are of different types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150340 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11Add support for implicit TLS model used with MS VC runtime.Anton Korobeynikov
Patch by Kai Nacke! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150307 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11Add TargetPassConfig hooks for scheduling/bundling.Andrew Trick
In case the MachineScheduling pass I'm working on doesn't work well for another target, they can completely override it. This also adds a hook immediately after the RegAlloc pass to cleanup immediately after vregs go away. We may want to fold it into the postRA hook later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150298 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11Allow Post-RA LICM to hoist reserved register reads.Jakob Stoklund Olesen
When using register masks, registers like %rip are clobbered by the register mask. LICM should still be able to hoist instructions reading %rip from a loop containing calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150288 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11Handle register masks in local live range splitting.Jakob Stoklund Olesen
Again the goal is to produce identical assembly with register mask operands enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150287 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11Don't read PreRegAlloc before it is initialized.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150286 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Add a static MachineOperand::clobbersPhysReg().Jakob Stoklund Olesen
It can be necessary to detach a register mask pointer from its MachineOperand. This method is convenient for checking clobbered physregs on a detached bitmask pointer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150261 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Add register mask support to InterferenceCache.Jakob Stoklund Olesen
This makes global live range splitting behave identically with and without register mask operands. This is not necessarily the best way of using register masks for live range splitting. It would be more efficient to first split global live ranges around calls (i.e., register masks), and reserve the fine grained per-physreg interference guidance for global live ranges that do not cross calls. For now the goal is to produce identical assembly when enabling register masks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150259 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Remove unused variable.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150258 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Put instruction names into an indexed string table on the side, removing a ↵Benjamin Kramer
pointer from MCInstrDesc. Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150245 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10comment grammarAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150233 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10RegAlloc superpass: includes phi elimination, coalescing, and scheduling.Andrew Trick
Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150226 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150225 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Remove unused 'isAlias' parameter.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150224 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Constrain the regmask search space for local live ranges.Jakob Stoklund Olesen
When checking a local live range for interference, restrict the binary search to the single block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150220 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Cache basic block boundaries for faster RegMaskSlots access.Jakob Stoklund Olesen
Provide API to get a list of register mask slots and bits in a basic block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150219 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Optimize LiveIntervals::intervalIsInOneMBB().Jakob Stoklund Olesen
No looping and binary searches necessary. Return a pointer to the containing block instead of just a bool. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150218 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Cache iterators. Some of these are expensive to create.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150214 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09Add register mask support to RAGreedy.Jakob Stoklund Olesen
This only adds the interference checks required for correctness. We still need to take advantage of register masks for the interference driven live range splitting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150191 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09Preserve physreg kills in MachineBasicBlock::SplitCriticalEdge.Lang Hames
Failure to preserve kills was causing LiveIntervals to miss some EFLAGS live ranges. Unfortunately I've been unable to reduce a good test case yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150152 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09Fix kill flags when moving instructions using LiveIntervals::moveInstr(...).Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150150 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09Remove assertion. Not all use operands are reads.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150149 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09Improve TargetPassConfig. No intended functionality.Andrew Trick
Split CodeGen into stages. Distinguish between optimization and correctness. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09commentAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150121 91177308-0d34-0410-b5e6-96231b3b80d8
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