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2012-04-01misched: Add finalizeScheduler to complete the target interface.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153827 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31Teach CodeGen's version of computeMaskedBits to understand the range metadata.Rafael Espindola
This is the CodeGen equivalent of r153747. I tested that there is not noticeable performance difference with any combination of -O0/-O2 /-g when compiling gcc as a single compilation unit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153817 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30If we have a VLA that has a "use" in a metadata node that's then usedBill Wendling
here but it has no other uses, then we have a problem. E.g., int foo (const int *x) { char a[*x]; return 0; } If we assign 'a' a vreg and fast isel later on has to use the selection DAG isel, it will want to copy the value to the vreg. However, there are no uses, which goes counter to what selection DAG isel expects. <rdar://problem/11134152> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153705 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Add support for objc property decls according to the page at:Eric Christopher
http://llvm.org/docs/SourceLevelDebugging.html#objcproperty including type and DECL. Expand the metadata needed accordingly. rdar://11144023 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153639 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Enable machine code verification in the entire code generator.Jakob Stoklund Olesen
Some targets still mess up the liveness information, but that isn't verified after MRI->invalidateLiveness(). The verifier can still check other useful things like register classes and CFG, so it should be enabled after all passes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153615 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Enable machine code verification after PreSched2 passes.Jakob Stoklund Olesen
The late scheduler depends on accurate liveness information if it is breaking anti-dependencies, so we should be able to verify it. Relax the terminator checking in the machine code verifier so it can handle the basic blocks created by if conversion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153614 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Also verify after ExpandPostRAPseudos.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153599 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Enable machine code verification after the late machine optimization passes.Jakob Stoklund Olesen
Branch folding invalidates liveness and disables liveness verification on some targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153597 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Skip liveness verification when MRI->tracksLiveness() is false.Jakob Stoklund Olesen
Extract the liveness verification into its own method. This makes it possible to run the machine code verifier after liveness information is no longer required to be valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153596 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Allow removeLiveIn to be called with a register that isn't live-in.Jakob Stoklund Olesen
This avoids the silly double search: if (isLiveIn(Reg)) removeLiveIn(Reg); git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153592 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Fixed commuteInstructions bug where if its called pre-regalloc the subreg ↵Pete Cooper
indices weren't commuted git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153579 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28More debug output.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153571 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Fix the output of the DW_TAG_friend tag to include DW_AT_friendEric Christopher
and not the rest of the member tag. Fixes PR11695 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153570 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27Use a SmallVector and linear lookup instead of a DenseSet - SourceMap valuesLang Hames
will always be tiny sets, so DenseSet is overkill (SmallSet won't work as we need iteration support). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153529 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27Use DW_AT_low_pc for a single entry point into a routine.Eric Christopher
Fixes PR10105 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153524 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27Print SSA and liveness tracking flags in MF::print().Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153518 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27Branch folding may invalidate liveness.Jakob Stoklund Olesen
Branch folding can use a register scavenger to update liveness information when required. Don't do that if liveness information is already invalid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153517 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27fix what looks like a real logic bug, found by PVS-Studio (part of PR12357)Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153513 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27Add an MRI::tracksLiveness() flag.Jakob Stoklund Olesen
Late optimization passes like branch folding and tail duplication can transform the machine code in a way that makes it expensive to keep the register liveness information up to date. There is a fuzzy line between register allocation and late scheduling where the liveness information degrades. The MRI::tracksLiveness() flag makes the line clear: While true, liveness information is accurate, and can be used for register scavenging. Once the flag is false, liveness information is not accurate, and can only be used as a hint. Late passes generally don't need the liveness information, but they will sometimes use the register scavenger to help update it. The scavenger enforces strict correctness, and we have to spend a lot of code to update register liveness that may never be used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153511 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27Post-ra LICM should take care not to hoist an instruction that would clobber aEvan Cheng
register that's read by the preheader terminator. rdar://11095580 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153492 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27During MachineCopyPropagation a register may be the source operand of multipleLang Hames
copies being considered for removal. Make sure to track all of the copies, rather than just the most recent encountered, by holding a DenseSet instead of an unsigned in SrcMap. No test case - couldn't reduce something with a sane size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153487 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-26Add a debug option to dump PBQP graphs during register allocation.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153483 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-26Use the file in the inlined die rather than the compile unit forEric Christopher
backtrace locations. Testcase forthcoming, but I wanted to get some testing here. Should fix: PR12323 PR12314 rdar://11091100 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153471 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-26No need to do an expensive stable sort for a bunch of integers.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153438 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-26Prune some includes and forward declarations.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153429 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-26Add a debug statement.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153428 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-24Add the ability to promote legal integer VAARGs. This is required for the ↵Hal Finkel
PPC64 SVR4 ABI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153372 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-23Pretty-printing comments for literal floating point in .s files.Jim Grosbach
Dump the hex representation to the comment stream as well as the float value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153346 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-23Add support for register masks to PBQP.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153341 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22Source order scheduler should not preschedule nodes with multiple uses. ↵Evan Cheng
rdar://11096639 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153270 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22Assign node orders to target intrinsics which do not produce results. ↵Evan Cheng
rdar://11096639 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153269 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22In erroneous inline assembly we could mistakenly try to access theEric Christopher
metadata operand as an actual operand, leading to an assert. Error out in this case. rdar://11007633 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153234 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22[fast-isel] Fold "urem x, pow2" -> "and x, pow2-1". This should fix the 271%Chad Rosier
execution-time regression for nsieve-bits on the ARMv7 -O0 -g nightly tester. This may also improve compile-time on architectures that would otherwise generate a libcall for urem (e.g., ARM) or fall back to the DAG selector. rdar://10810716 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153230 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21Checking a build_vector for an all-ones value.Jim Grosbach
Type legalization can zero-extend the elements of the build_vector node, so, for example, we may have an <8 x i8> with i32 elements of value 255. That should return 'true' for the vector being all ones. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153203 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21misched: fix LiveInterval update for bottom-up schedulingAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153162 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21misched: trace LiveIntervals after scheduling.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153161 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21misched: obvious iterator update fixes for bottom-up.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153160 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21misched: cleanup main loopAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153159 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21misched: fix LI update for bottom-up.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153158 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20It's possible to have a constant expression who's size is quite big (e.g.,Bill Wendling
i128). In that case, we may not be able to print out the MCExpr as an expression. For instance, we could have an MCExpr like this: 0xBEEF0000BEEF0000 | (0xBEEF0000BEEF0000 << 64) The MCExpr printer handles sizes up to 64-bits, but this expression would require 128-bits. In this situation, try to evaluate the constant expression and emit that as the value into 64-bit chunks. <rdar://problem/11070338> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153081 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20When combining (vextract shuffle (load ), <1,u,u,u>), 0) -> (load ), add ↵Craig Topper
users of the final load to the worklist too. Needed by changes I'm preparing to make to X86 backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153078 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Do everything up to generating code to try to get a register forEric Christopher
a variable. The previous code would break the debug info changing code invariant. This will regress debug info for arguments where we elide the alloca created. Fixes rdar://11066468 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153074 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Untabify.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153073 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Add another debugging statement here.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153072 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Use lookUpRegForValue here instead of duplicating the code.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153071 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19f16 FDIV can now be legalized by promoting to f32Pete Cooper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153064 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19Add an option to the MI scheduler to cut off scheduling after a fixed number ofLang Hames
instructions have been scheduled. Handy for tracking down scheduler bugs, or bugs exposed by scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153045 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19Fix DAG combine which creates illegal vector shuffles. Patch by Heikki Kultala.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153035 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17CriticalAntiDepBreaker: Replace a SmallSet of regs with a much denser BitVector.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152999 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17MachineInstr: Inline the fast path (non-bundle instruction) of hasProperty.Benjamin Kramer
This is particularly helpful as both arguments tend to be constants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152991 91177308-0d34-0410-b5e6-96231b3b80d8
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