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2012-06-22Remove LiveIntervals::trackingRegUnits().Jakob Stoklund Olesen
With regunit liveness permanently enabled, this function would always return true. Also remove now obsolete code for checking physreg interference. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159006 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22Remove another duplicated variable. We only need one to tell us if the linkerRafael Espindola
knows dwarf or not. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158993 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22Fix a FIXME: DwarfRequiresRelocationForSectionOffset is the same asRafael Espindola
DwarfUsesRelocationsAcrossSections. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158992 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22Emit relocations for DW_AT_location entries on systems which need it. This isNick Lewycky
a recommit of r127757. Fixes PR9493. Patch by Paul Robinson! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158957 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22Rename -allow-excess-fp-precision flag to -fuse-fp-ops, and switch from aLang Hames
boolean flag to an enum: { Fast, Standard, Strict } (default = Standard). This option controls the creation by optimizations of fused FP ops that store intermediate results in higher precision than IEEE allows (E.g. FMAs). The behavior of this option is intended to match the behaviour specified by a soon-to-be-introduced frontend flag: '-ffuse-fp-ops'. Fast mode - allows formation of fused FP ops whenever they're profitable. Standard mode - allow fusion only for 'blessed' FP ops. At present the only blessed op is the fmuladd intrinsic. In the future more blessed ops may be added. Strict mode - allow fusion only if/when it can be proven that the excess precision won't effect the result. Note: This option only controls formation of fused ops by the optimizers. Fused operations that are explicitly requested (e.g. FMA via the llvm.fma.* intrinsic) will always be honored, regardless of the value of this option. Internally TargetOptions::AllowExcessFPPrecision has been replaced by TargetOptions::AllowFPOpFusion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158956 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-21The inline asm operand modifier 'n' is suppose Jack Carter
to be generic across architectures. It has the following description in the gnu sources: Negate the immediate constant Several Architectures such as x86 have local implementations of operand modifier 'n' which go beyond the above description slightly. This won't affect them. Affected files: lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Added 'n' to the switch cases. test/CodeGen/Generic/asm-large-immediate.ll Generic compiled test (x86 for me) test/CodeGen/Mips/asm-large-immediate.ll Mips compiled version of the generic one Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158939 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-21Fix potential crash if DAGCombine on stores sees a half typePete Cooper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158927 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-21The inline asm operand modifier 'c' is suppose Jack Carter
to be generic across architectures. It has the following description in the gnu sources: Substitute immediate value without immediate syntax Several Architectures such as x86 have local implementations of operand modifier 'c' which go beyond the above description slightly. To make use of the generic modifiers without overriding local implementation one can make a call to the base class method for AsmPrinter::PrintAsmOperand() in the locally derived method's "default" case in the switch statement. That way if it is already defined locally the generic version will never get called. This change is needed when test/CodeGen/generic/asm-large-immediate.ll failed on a native Mips board. The test was assuming a generic implementation was in place. Affected files: lib/Target/Mips/MipsAsmPrinter.cpp: Changed the default case to call the base method. lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Added 'c' to the switch cases. test/CodeGen/Mips/asm-large-immediate.ll Mips compiled version of the generic one Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158925 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-21Emit a single _udivmodsi4 libcall instead of two separate _udivsi3 andEvan Cheng
_umodsi3 libcalls if they have the same arguments. This optimization was apparently broken if one of the node was replaced in place. rdar://11714607 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158900 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-21Update regunits in RegisterCoalescer::reMaterializeTrivialDef.Jakob Stoklund Olesen
Old code would only update physreg live intervals. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158881 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Remove spurious typedefs.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158878 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Remove the RenderMachineFunction HTML output pass.Jakob Stoklund Olesen
I don't think anyone has been using this functionality for a while, and it is getting in the way of refactoring now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158876 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Remove the -live-regunits command line option.Jakob Stoklund Olesen
Register allocators depend on it being permanently enabled now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158873 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Fix some more LiveInterval enumerations.Jakob Stoklund Olesen
Deterministically enumerate the virtual registers instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158872 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Remove LiveIntervalUnions from RegAllocBase.Jakob Stoklund Olesen
They are living in LiveRegMatrix now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158868 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Convert RAGreedy to LiveRegMatrix interference checking.Jakob Stoklund Olesen
Stop depending on the LiveIntervalUnions in RegAllocBase, they are about to be removed. The changes are mostly replacing register alias iterators with regunit iterators, and querying LiveRegMatrix instrad of RegAllocBase. InterferenceCache is converted to work with per-regunit LiveIntervalUnions, and it checks fixed regunit interference separately, using the fixed live intervals provided by LiveIntervalAnalysis. The local splitting helper calcGapWeights() is also considering fixed regunit interference which is kept on the side now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158867 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Convert RABasic to using LiveRegMatrix interference checking.Jakob Stoklund Olesen
Stop using the LiveIntervalUnions provided by RegAllocBase, they will be removed soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158866 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Enable register unit liveness by default.Jakob Stoklund Olesen
Soon we won't need to compute live intervals for physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158865 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Teach PBQPBuilder::build() about regunit interference.Jakob Stoklund Olesen
Filter out physreg candidates with regunit interferrence. Also compute regmask interference more efficiently. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158864 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Avoid iterating with LiveIntervals::iterator.Jakob Stoklund Olesen
That is a DenseMap iterator keyed by pointers, so the iteration order is nondeterministic. I would like to replace the DenseMap with an IndexedMap which doesn't allow iteration. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158856 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Add users of a MERGE_VALUE node to the worklist to process again when the ↵Pete Cooper
node is removed. Sorry, no test case. Foudn it by inspection of the code git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158839 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Only update regunit live ranges that have been precomputed.Jakob Stoklund Olesen
Regunit live ranges are computed on demand, so when mi-sched calls handleMove, some regunits may not have live ranges yet. That makes updating them easier: Just skip the non-existing ranges. They will be computed correctly from the rescheduled machine code when they are needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158831 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Delete dead code.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158827 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Fix DAGCombine to deal with ext-conversion of pre/post_inc loads.Hal Finkel
The test case for this will come with the PPC indexed preinc loads commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158822 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Fixing a compiler warning in MSVC 10.Aaron Ballman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158820 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Fix two rather subtle internal vs. external linker issues.Chandler Carruth
I'll admit I'm not entirely satisfied with this change, but it seemed the cleanest option. Other suggestions quite welcome The issue is that the traits specializations have static methods which return the typedef'ed PHI_iterator type. In both the IR and MI layers this is typedef'ed to a custom iterator class defined in an anonymous namespace giving the types and the functions returning them internal linkage. However, because the traits specialization is defined in the 'llvm' namespace (where it has to be, specialized template lives there), and is in turn used in the templated implementation of the SSAUpdater. This led to the linkage conflict that Clang now warns about. The simplest solution to me was just to define the PHI_iterator as a nested class inside the trait specialization. That way it still doesn't get scoped widely, it can't be accidentally reused somewhere, etc. This is a little gross just because nested class definitions are a little gross, but the alternatives seem more ad-hoc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158799 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20A new algorithm for computing LoopInfo. Temporarily disabled.Andrew Trick
-stable-loops enables a new algorithm for generating the Loop forest. It differs from the original algorithm in a few respects: - Not determined by use-list order. - Initially guarantees RPO order of block and subloops. - Linear in the number of CFG edges. - Nonrecursive. I didn't want to change the LoopInfo API yet, so the block lists are still inclusive. This seems strange to me, and it means that building LoopInfo is not strictly linear, but it may not be a problem in practice. At least the block lists start out in RPO order now. In the future we may add an attribute or wrapper analysis that allows other passes to assume RPO order. The primary motivation of this work was not to optimize LoopInfo, but to allow reproducing performance issues by decomposing the compilation stages. I'm often unable to do this with the current LoopInfo, because the loop tree order determines Loop pass order. Serializing the IR tends to invert the order, which reverses the optimization order. This makes it nearly impossible to debug interdependent loop optimizations such as LSR. I also believe this will provide more stable performance results across time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158790 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Move the implementation of LoopInfo into LoopInfoImpl.h.Andrew Trick
The implementation only needs inclusion from LoopInfo.cpp and MachineLoopInfo.cpp. Clients of the interface should only include the interface. This makes the interface readable and speeds up rebuilds after modifying the implementation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158787 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Add regunit liveness support to LiveIntervals::handleMove().Jakob Stoklund Olesen
When LiveIntervals is tracking fixed interference in regunits, make sure to update those intervals as well. Currently guarded by -live-regunits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158766 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Tidy up.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158762 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Add an ensureMaxAlignment() function to MachineFrameInfo (analogous toChad Rosier
ensureAlignment() in MachineFunction). Also, drop setMaxAlignment() in favor of this new function. This creates a main entry point to setting MaxAlignment, which will be helpful for future work. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158758 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Add DAG-combines for aggressive FMA formation.Lang Hames
This patch adds DAG combines to form FMAs from pairs of FADD + FMUL or FSUB + FMUL. The combines are performed when: (a) Either AllowExcessFPPrecision option (-enable-excess-fp-precision for llc) OR UnsafeFPMath option (-enable-unsafe-fp-math) are set, and (b) TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) is true for the type of the FADD/FSUB, and (c) The FMUL only has one user (the FADD/FSUB). If your target has fast FMA instructions you can make use of these combines by overriding TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) to return true for types supported by your FMA instruction, and adding patterns to match ISD::FMA to your FMA instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158757 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-1980 col.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158755 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Implement PPCInstrInfo::isCoalescableExtInstr().Jakob Stoklund Olesen
The PPC::EXTSW instruction preserves the low 32 bits of its input, just like some of the x86 instructions. Use it to reduce register pressure when the low 32 bits have multiple uses. This requires a small change to PeepholeOptimizer since EXTSW takes a 64-bit input register. This is related to PR5997. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158743 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Style: Don't reuse variables for multiple purposes.Jakob Stoklund Olesen
No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158742 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Move the support for using .init_array from ARM to the genericRafael Espindola
TargetLoweringObjectFileELF. Use this to support it on X86. Unlike ARM, on X86 it is not easy to find out if .init_array should be used or not, so the decision is made via TargetOptions and defaults to off. Add a command line option to llc that enables it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158692 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-18Allow up to 64 functional units per processor itinerary.Hal Finkel
This patch changes the type used to hold the FU bitset from unsigned to uint64_t. This will be needed for some upcoming PowerPC itineraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158679 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-16Guard private fields that are unused in Release builds with #ifndef NDEBUG.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158608 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-15Remove final verification in RABasic.Jakob Stoklund Olesen
We now have a proper machine code verifier pass between register allocation and rewriting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158577 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-15Print out register number in InlineSpiller.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158575 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-15Accept null PhysReg arguments to checkRegMaskInterference.Jakob Stoklund Olesen
Calling checkRegMaskInterference(VirtReg) checks if VirtReg crosses any regmask operands, regardless of the registers they clobber. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158563 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-15Remove assignments which aren't used afterwards.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158535 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-15Use regunit liveness in RegisterCoalescer when it is available.Jakob Stoklund Olesen
We only do very limited physreg coalescing now, but we still merge virtual registers into reserved registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158526 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-14Make machine verifier check the first instruction of the last bundle instead ofAkira Hatanaka
the last instruction of a basic block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158468 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-14Make comment slightly more helpful.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158467 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-14misched: disable SSA check pending PR13112.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158461 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-13sched: fix latency of memory dependence chain edges for consistency.Andrew Trick
For store->load dependencies that may alias, we should always use TrueMemOrderLatency, which may eventually become a subtarget hook. In effect, we should guarantee at least TrueMemOrderLatency on at least one DAG path from a store to a may-alias load. This should fix the standard mode as well as -enable-aa-sched-mi". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158380 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-13sched: Avoid trivially redundant DAG edges. Take the one with higher latency.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158379 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-11misched: When querying RegisterPressureTracker, always save current and max ↵Andrew Trick
pressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158340 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-11misched: regpressure getMaxPressureDelta, revert accidental checkin.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158339 91177308-0d34-0410-b5e6-96231b3b80d8
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